EPM9320ARC208-10N vs EPM9320RC208-10 Comparison
Detailed side-by-side comparison of EPM9320ARC208-10N by Altera and EPM9320RC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ARC208-10N | EPM9320RC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 320 | — |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | [DATA_NEEDED: LAB count] |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | — |
| Dedicated Input Pins | 12 | — |
| Package | 208-pin RQFP (BFQFP with exposed pad) | 208-pin RQFP (RC) |
| Mounting Type | Surface Mount | — |
| Operating Temperature | 0C to +70C (Commercial) | Commercial (0C to +70C) - 'C' suffix |
| Programming Interface | IEEE Std. 1149.1 JTAG | JTAG (ByteBlaster/BitBlaster) |
| Configuration Memory | Non-volatile EEPROM | — |
| RoHS Status | Compliant (lead-free 'N' suffix) | ROHS3 Compliant (per fpgalink listing) |
| Usable Gates | — | 6,000 |
| Macrocells | — | 320 |
| Supply Voltage | — | 5 V |
| Speed Grade | — | -10 |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Moisture Sensitivity Level (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |