EPM9320ARI208-10N vs EPM9320AR1208-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ARI208-10N sa pamamagitan ng Altera at EPM9320AR1208-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320ARI208-10N EPM9320AR1208-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 —
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 6,000 —
Macrocells 320 [DATA_NEEDED: macrocell count]
Logic Array Blocks (LABs) 20 [DATA_NEEDED: LAB count]
Maximum Operating Frequency 144.9 MHz —
Propagation Delay (tPD) 10 ns (speed grade -10) —
Volte ng Pagbibigay 4.5 V to 5.5 V 5 V (typical)
Temperature na Operasyon -40 C to +85 C (industrial) [DATA_NEEDED: commercial/industrial/military grade]
Packhaging 208-pin RQFP (S-PQFP-G208) —
Uri ng Pagpapasok Surface Mount Through-Hole (Pin Grid Array socket)
Process Technology CMOS EEPROM 0.7 µm CMOS EEPROM
Programmability In-system (ISP) via IEEE 1149.1 JTAG —
Global Dedicated Inputs 16 —
Architecture Multiple Array MatriX (MAX) third-generation —
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance - legacy part]
Product Family — MAX 9000
Device Type — EPLD (Erasable Programmable Logic Device)
Logic Density — 6,000 usable gates
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX in MHz]
Package Type — PGA-1208 (Pin Grid Array)
Package Code — AR1208
Bilang ng Pin — 1208
Programming Interface — IEEE 1149.1 JTAG (ByteBlaster compatible)
Lead-Free — [DATA_NEEDED: lead-free status]

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