EPM9320ARI208-10N vs EPM9320AR1208-10 比較
詳細並排比較 EPM9320ARI208-10N 由 Altera 與 EPM9320AR1208-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteAltera
EPM9320AR1208-10 - MAX 9000 EPLD, 1208-Pin PGA, 10ns | Intel / Altera
EPM9320AR1208-10 Obsolete規格比較
| 參數 | EPM9320ARI208-10N | EPM9320AR1208-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | — |
| Macrocells | 320 | [DATA_NEEDED: macrocell count] |
| Logic Array Blocks (LABs) | 20 | [DATA_NEEDED: LAB count] |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| 供應電壓 | 4.5 V to 5.5 V | 5 V (typical) |
| 工作溫度 | -40 C to +85 C (industrial) | [DATA_NEEDED: commercial/industrial/military grade] |
| 封裝 | 208-pin RQFP (S-PQFP-G208) | — |
| 安裝類型 | Surface Mount | Through-Hole (Pin Grid Array socket) |
| Process Technology | CMOS EEPROM | 0.7 µm CMOS EEPROM |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance - legacy part] |
| Product Family | — | MAX 9000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Density | — | 6,000 usable gates |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX in MHz] |
| Package Type | — | PGA-1208 (Pin Grid Array) |
| Package Code | — | AR1208 |
| 腳位數 | — | 1208 |
| Programming Interface | — | IEEE 1149.1 JTAG (ByteBlaster compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |