EPM9320ARI208-10N vs EPM9320RI208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ARI208-10N sa pamamagitan ng Altera at EPM9320RI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoletePagsanggunian na paghahambing
| Parametro | EPM9320ARI208-10N | EPM9320RI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 20 |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Volte ng Pagbibigay | 4.5 V to 5.5 V | 5 V |
| Temperature na Operasyon | -40 C to +85 C (industrial) | — |
| Packhaging | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (PowerQuad II) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| Tindminan RoHS | unknown | Compliant (N suffix = lead-free) |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 320 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum System Clock Frequency | — | 100 MHz |
| I/O Voltage | — | 5 V |
| User I/O Pins | — | 160 |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG/ISP) |
| Hanay ng Temperature na Operasyon | — | -40C to +85C (industrial) |
| Lead Finish | — | Lead-free (matte tin) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |