EPM9320LC84-10 vs EPM9320LI84-20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-10 sa pamamagitan ng Intel at EPM9320LI84-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320LC84-10 | EPM9320LI84-20N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | 6,000 to 12,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 168 (varies by package) | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | — |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM | Advanced CMOS EEPROM |
| Packhaging | 84-pin PLCC (JEDEC MO-047) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket also common) | — |
| Temperature na Operasyon | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | 0 C to +70 C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | IEEE 1149.1 JTAG, in-system programmable |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS compliance status] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | MSL-3, 168 hours (per fpgalink listing) | — |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 60 |
| Total Pins | — | 84 |
| Propagation Delay (tPD) | — | 20 ns (speed grade -20) |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | — | 118 MHz |
| Logic Family | — | CMOS, EEPROM-based |
| Volte ng Pagbibigay | — | 5.0 V |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |