EPM9320RC208-10 vs EPM9320RC208-20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-10 sa pamamagitan ng Altera at EPM9320RC208-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320RC208-10 | EPM9320RC208-20N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Packhaging | 208-pin RQFP (RC) | 208-pin RQFP (PowerQuad II) |
| Temperature na Operasyon | Commercial (0C to +70C) - 'C' suffix | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | 5 V | 5.0 V |
| Speed Grade | -10 | — |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) | — |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) | — |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Device Family | — | MAX 9000 |
| Logic Type | — | Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 320 |
| Logic Array Blocks | — | 20 |
| Maximum Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| User I/O Pins | — | 168 |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |