EPM9320RC208-20 vs EPM9320RC208-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-20 sa pamamagitan ng Altera at EPM9320RC208-15N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320RC208-20 | EPM9320RC208-15N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Usable Gates | 6,000 | 6,000 |
| Maximum I/O Pins | 132 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Programming Technology | EEPROM, in-system programmable (ISP) | — |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | — |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | — |
| Packhaging | 208-RQFP, exposed pad (208-BFQFP) | 208-pin RQFP (PowerQuad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | — |
| Process Technology | CMOS, 5.0 V EEPROM | — |
| Reprogrammability | Yes, unlimited ISP cycles | — |
| Macro Cells | — | 320 |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Propagation Delay (tPD) | — | 15 ns |
| Maksimum na Taktiko ng Oras | — | 117.6 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Technology | — | CMOS EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Terminal Pitch | — | 0.5 mm |
| Hanay ng Temperature na Operasyon | — | 0C to +70C (commercial) |
| Packaging | — | Tray |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |