EPM9320RI208-10N vs EPM9320RI208-20C Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RI208-10N sa pamamagitan ng Altera at EPM9320RI208-20C sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM9320RI208-10N EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera

EPM9320RI208-10N ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro EPM9320RI208-10N EPM9320RI208-20C
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Family MAX 9000 MAX 9000
Device Type Complex Programmable Logic Device (CPLD) EE PLD / CPLD
Usable Gates 6,000 6,000
Macro Cells 320 —
Logic Array Blocks (LABs) 20 16
Pin-to-Pin Propagation Delay (tPD) 10 ns 20 ns
Maximum System Clock Frequency 100 MHz —
Volte ng Pagbibigay 5 V —
I/O Voltage 5 V —
User I/O Pins 160 —
Packhaging 208-pin RQFP (PowerQuad II) 208-pin RQFP (Plastic Quad Flat Pack)
Uri ng Pagpapasok Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes (JTAG/ISP) Yes (5.0 V ISP via JTAG)
Hanay ng Temperature na Operasyon -40C to +85C (industrial) —
Tindminan RoHS Compliant (N suffix = lead-free) —
Lead Finish Lead-free (matte tin) —
Level ng MSL [DATA_NEEDED: MSL level] —
Logic Elements / Macrocells — 320
Number of Flip-Flops — 484
Maximum Internal Clock Frequency — 100 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5.0 V
Programmable Interface — JTAG (IEEE Std. 1149.1) BST
Technology — CMOS EEPROM
Operating Temperature (Industrial) — -40C to +85C
Lead-Free / RoHS — Information not confirmed from verified data [DATA_NEEDED: RoHS status]

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