EPM9560ARC208-10N vs EPM9560ARI240-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARC208-10N sa pamamagitan ng Altera at EPM9560ARI240-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560ARC208-10N | EPM9560ARI240-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| User I/O Pins | 153 | 191 |
| Pin-to-Pin Delay | 10 ns | — |
| Internal Counter Frequency | 144.9 MHz | — |
| Volte ng Pagbibigay | 5 V | 5.0 V |
| Technology | CMOS EEPROM | CMOS, EEPROM-based configuration |
| Packhaging | 208-pin RQFP (PowerQuad II) | 240-pin RQFP (PowerQuad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 C to +70 C (commercial) | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile, instant-on) |
| In-System Programmability | Yes (JTAG ISP) | — |
| Logic Array Blocks (LABs) | 20 | — |
| Speed Grade | -10 | — |
| Tindminan RoHS | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 560 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Internal Frequency | — | 144.9 MHz |
| Hanay ng Temperature na Operasyon | — | -40 C to +85 C (industrial) |
| Logic Architecture | — | Multiple Array MatriX (MAX) with global interconnect array |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |
| Number of Terminals | — | 240 |
| Terminal Form | — | Gull Wing |