EPM9560ARC240-10 vs EPM9560GC280-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARC240-10 sa pamamagitan ng Altera at EPM9560GC280-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560ARC240-10 EPM9560GC280-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) EE PLD (CMOS EEPROM-based CPLD)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX)
Usable Gates 12,000 —
Macrocells 560 —
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz —
Propagation Delay (tpd) 11.4 ns 15 ns (speed grade -15)
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM —
Packhaging 240-pin PowerQuad QFP (RQFP / EAR240) —
Temperature na Operasyon 0C to +70C (commercial) —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
Logic Family CMOS —
Tindminan RoHS [DATA_NEEDED: RoHS status] Non-compliant (ceramic CPGA, contains lead)
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Uri ng Pagpapasok — Through-Hole
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Katayuan ng Lifecycle — Obsolete (legacy Altera MAX 9000 family)

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