EPM9560GI280-15 vs EPM9560GI280-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GI280-15 sa pamamagitan ng Intel at EPM9560GI280-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560GI280-15 | EPM9560GI280-20 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | 772 |
| User I/Os | 216 | — |
| Dedicated Inputs | 12 | — |
| Logic Elements / Gates | 12,000 usable gates | — |
| Internal Frequency (fMAX) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns | — |
| Clock-to-Output (tCO) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (3.3 V or 5 V I/O) | — |
| In-System Programmability | 5.0-V ISP via JTAG | Yes (IEEE Std. 1149.1 JTAG) |
| Packhaging | 280-pin PGA (ceramic, metal-sealed cofired) | 280-pin PGA (PIN/PEG, square) |
| Temperature na Operasyon | -40 °C to 85 °C (industrial) | — |
| Process Technology | CMOS EEPROM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | MSL-3 (168 hours) | — |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 28 (16 macrocells each) |
| Usable Gates | — | 12,000 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programming Technology | — | EEPROM (non-volatile) |
| Terminal Form | — | PIN/PEG (through-hole PGA) |
| Package Code | — | PGA |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |