EPM9560GM280-15 vs EPM9560GC280-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GM280-15 sa pamamagitan ng Altera at EPM9560GC280-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560GM280-15 EPM9560GC280-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 9000 MAX 9000
Device Type EE PLD (EEPROM-based) EE PLD (CMOS EEPROM-based CPLD)
Macrocells 560 —
Flip-Flops 772 —
User I/O 216 —
Logic Array Blocks (LABs) 35 (16 macrocells each) —
Supply Voltage (Nominal) 5.0 V —
Supply Voltage (Max) 5.5 V —
I/O Logic Level Support 3.3 V or 5 V —
Pin-to-Pin Delay (tPD) 15 ns (speed grade -15) —
Packhaging FineLine BGA-280 (GM) —
Process Technology CMOS EEPROM —
In-System Programmability Yes (5V ISP via JTAG IEEE 1149.1) —
Temperature na Operasyon -40C to +85C (industrial) —
Tindminan RoHS ROHS3 Compliant Non-compliant (ceramic CPGA, contains lead)
Level ng MSL 3 (168 Hours) —
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Uri ng Pagpapasok — Through-Hole
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Architecture — Multiple Array MatriX (MAX)
Katayuan ng Lifecycle — Obsolete (legacy Altera MAX 9000 family)

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