EPM9560R1208-20 vs EPM9560GC280-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560R1208-20 sa pamamagitan ng Altera at EPM9560GC280-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560R1208-20 EPM9560GC280-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 6,000 12,000
Macrocells 560 560
Logic Array Blocks 52 (typical for 560 macrocells) —
Maximum User I/O 212 212
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Technology CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: commercial/industrial/military grade]
Packhaging R-1208 (BGA-style fine-pitch) 280-pin CPGA (Ceramic Pin Grid Array)
Uri ng Pagpapasok Surface Mount Through-Hole (CPGA socket)
Process Technology CMOS EEPROM, third-generation MAX architecture CMOS EEPROM
Architecture Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) —
Boundary-Scan Test JTAG IEEE Std. 1149.1 —
Configuration Memory On-chip EEPROM (non-volatile) —
Tindminan RoHS [DATA_NEEDED: confirm via current distributor data] [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant]
Pin-to-Pin Delay — 20 ns (speed grade -20)
Counter Frequency (max) — 100 MHz
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
I/O Voltage — 3.3 V or 5.0 V configurable
In-System Programming — Yes, via IEEE 1149.1 JTAG

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