EPM9560RC208-20 vs EPM9560RC208-18 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-20 sa pamamagitan ng Intel at EPM9560RC208-18 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-20 | EPM9560RC208-18 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Tapus ng Buhay |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Macrocells | 560 | 560 macrocells |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks | 35 | — |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maksimum na Taktiko ng Oras | 100 MHz | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Packhaging | 208-pin RQFP (28x28 mm) | 208-pin RQFP (Power Quad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Standards | 5.0 V TTL/CMOS compatible | — |
| Flip-Flops | 772 | 772 flip-flops |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Propagation Delay (tPD) | — | 18 ns (speed grade -18) |
| Maximum Operating Frequency | — | 117.6 MHz (family -15 grade reference) |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| User I/O Lines | — | 149 I/O lines |
| Package JESD-30 Code | — | S-PQFP-G208 |
| Configuration Memory | — | EEPROM (non-volatile, no external config PROM) |
| Technology | — | CMOS |
| Katayuan ng Lifecycle | — | EOL / mature (per Altera product discontinuance notice) |