EPM9560RC208-20N vs EPM9560WC208-20C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-20N sa pamamagitan ng Intel at EPM9560WC208-20C sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-20N | EPM9560WC208-20C |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EE PLD) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Packhaging | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| User I/O Pins | 149 | 149 |
| Volte ng Pagbibigay | 5.0 V | 3.3 V or 5 V (configurable I/O) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (Ceramic QFP) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Tindminan RoHS | Lead-free (N suffix) | ROHS3 Compliant (per fpgalink listing) |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | EPM9560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maksimum na Taktiko ng Oras | — | [DATA_NEEDED: fMAX value not in verified data] |
| Process Technology | — | CMOS, Electrically Erasable |
| Bilang ng Pin | — | 208 |
| Programming Interface | — | JTAG BST (in-system programmable) |
| Operating Temperature Grade | — | Commercial (C suffix) |
| Moisture Sensitivity Level | — | MSL 3 (168 Hours) |