EPM9560RC240-15C vs EPM9560RC240-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-15C sa pamamagitan ng Intel at EPM9560RC240-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC240-15C | EPM9560RC240-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | Complex Programmable Logic Device (CPLD) |
| Usable Gates | 12,000 | 12,000 gates |
| Macrocells | 560 | — |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | 192 |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| Operating Voltage Range | 3.3 V or 5 V | — |
| Packhaging | 240-pin RQFP (PowerQuad II) | 240-pin RQFP (PowerQuad) |
| Terminal Pitch | 0.5 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 12 |
| Maximum System Frequency | — | 144.9 MHz |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Technology | — | CMOS EEPROM |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 (168 Hours) |
| Configuration Memory | — | Non-volatile EEPROM (instant-on) |
| Manufacturer Standard Lead Time | — | 1-7 Days (distributor stock) |