EPM9560RC240-15N vs EPM9560RC240-15C Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-15N sa pamamagitan ng Altera at EPM9560RC240-15C sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC240-15N EPM9560RC240-15C
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Series MAX 9000 —
Family MAX 9000 (third-generation Multiple Array MatriX) MAX 9000
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 35 —
Maximum User I/O Pins 216 —
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Internal Counter Frequency (fCNT) 145 MHz —
Global Setup Time (tFSU) [DATA_NEEDED: tFSU for -15 grade] —
Clock-to-Output Time (tFCO) [DATA_NEEDED: tFCO for -15 grade] —
Volte ng Pagbibigay 5.0 V 5.0 V
Logic Family CMOS (EEPROM-based) —
Programmability In-system programmable (IEEE 1532/JTAG) —
Boundary-Scan Test JTAG (IEEE 1149.1) —
Temperature na Operasyon 0C to +70C (Commercial) 0C to +70C (Commercial)
Packhaging RQFP-240 (240-pin Plastic Quad Flat Pack) 240-pin RQFP (PowerQuad II)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance - older Altera RQFP part] [DATA_NEEDED: RoHS status]
Device Type — EEPROM-based CPLD
Logic Array Blocks — 20
User I/O Pins — 187
Maximum Internal Frequency — 117.6 MHz
Propagation Delay (tPD) — 15 ns
Operating Voltage Range — 3.3 V or 5 V
Terminal Pitch — 0.5 mm
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes (ISP via JTAG)
JTAG Interface — IEEE 1149.1 boundary-scan
Process Technology — CMOS
Level ng MSL — [DATA_NEEDED: MSL level]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita