EPM9560RC304-15F vs EPM9560RC304-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC304-15F sa pamamagitan ng Altera at EPM9560RC304-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteIntel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560RC304-15F | EPM9560RC304-2 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000 | — |
| Series | EPM9560 | — |
| Macrocells | 560 | [DATA_NEEDED: macrocell count] |
| Usable Gates | 12,000 | Approximately 12,000 |
| Propagation Delay (tpd) | 16.6 ns (max) | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Core Supply Voltage | 5.0 V | 5.0 V |
| User I/O Pins | 212 | 304 |
| Dedicated Inputs | 4 | — |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | 16 |
| Packhaging | RQFP-304 (304-pin Plastic QFP) | 304-pin RQFP (RC) |
| Programming Technology | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) | EEPROM (in-system programmable) |
| Architecture | Multiple Array MatriX (MAX) with PIA interconnect | Multiple Array MatriX (MAX) - third generation |
| Boundary Scan Test (BST) | Yes, JTAG-compliant | — |
| Temperature na Operasyon | -40C to +85C (industrial) | Commercial (0C to +70C) |
| Process Technology | High-performance CMOS, EEPROM-based | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (168 hours) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status - not stated in source] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (EPLD - Erasable PLD) |
| Speed Grade | — | -2 |
| I/O Supply Voltage | — | 5.0 V |
| JTAG Support | — | IEEE Std. 1149.1 (boundary-scan + ISP) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |