EPM9560RC304-5 vs EPM9560RCRC304-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC304-5 sa pamamagitan ng Altera at EPM9560RCRC304-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC304-5 | EPM9560RCRC304-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 (EPM9560) |
| Device Type | Complex Programmable Logic Device (CPLD) / EPLD | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| Volte ng Pagbibigay | 5.0 V | 5.0 V |
| Speed Grade | -5 (fastest grade in family) | — |
| Packhaging | 304-pin RQFP (PowerQuad II) | 304-pin RQFP (PowerQuad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG ISP) | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 Hours) | — |
| Tindminan RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Manufacturer Standard Lead Time | 1-7 Days (distributor listing) | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Propagation Delay (tPD) | [DATA_NEEDED: propagation delay] | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: number of LABs] | [DATA_NEEDED: LAB count] |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 117.6 MHz |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| In-System Programmability (ISP) | — | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 (built-in) |
| Number of User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |
| Lead Finish | — | [DATA_NEEDED: lead finish] |