EPM9560RC340-15 vs EPM9560RC304-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC340-15 sa pamamagitan ng Altera at EPM9560RC304-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC340-15 EPM9560RC304-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 560
Usable Gates 12,000 12,000
Pin-to-Pin Delay (tPD) 15 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5.0 V nominal) —
User I/O Pins 212 —
Packhaging 340-RQFP (Reduced Quad Flat Pack) 304-pin RQFP
Uri ng Pagpapasok Surface Mount Surface Mount
Process Technology CMOS EEPROM —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
Operating Temperature (Commercial) 0C to +70C —
Architecture Multiple Array MatriX (MAX) - 3rd generation —
Boundary Scan IEEE Std. 1149.1 JTAG —
Programming Technology EEPROM (non-volatile, reprogrammable) —
Tindminan RoHS [DATA_NEEDED: RoHS status - not explicitly stated in verified data] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family — MAX 9000 (EPM9560)
User I/O Lines — 212
Propagation Delay (tPD) — 20 ns
Maximum Operating Frequency — 100 MHz
Core Supply Voltage — 5.0 V
I/O Voltage — 3.3 V or 5 V (configurable)
Configuration Technology — EEPROM (in-system programmable)
JTAG Interface — IEEE Std. 1149.1 (built-in)
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Logic Array Blocks (LABs) — 20
Speed Grade — -20
Level ng MSL — [DATA_NEEDED: MSL level]

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