EPM9560RI208-10N vs EPM9560RI208-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-10N sa pamamagitan ng Altera at EPM9560RI208-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-10N | EPM9560RI208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX), 3rd generation |
| Usable Gates | 12,000 | — |
| Macro Cells | 560 | — |
| Register Bits | 12,160 | — |
| User I/Os | 212 | 216 (per DigiChip specification; see _validation_note) |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Maximum Frequency | 100 MHz to 125 MHz | — |
| Volte ng Pagbibigay | 5 V | 5.0 V |
| Packhaging | 208-pin RQFP (PQFP) | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Temperature na Operasyon | -40C to +85C (Industrial grade, "RI" suffix) | 0C to 70C (Commercial) |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | — |
| Level ng MSL | 3 (168 Hours) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink) | [DATA_NEEDED: RoHS status] |
| Configuration Memory | On-chip EEPROM (non-volatile) | CMOS EEPROM, in-system programmable |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Speed Grade | — | -15 |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |