EPM9560RI208-20N vs EPM9560TC208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-20N sa pamamagitan ng Intel at EPM9560TC208-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-20N | EPM9560TC208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | 12000 |
| Macrocells | 560 | 560 |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | — |
| Counter Speed | 100 MHz | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Packhaging | 208-pin RQFP | TQFP-208 (TC208) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | Industrial (-40C to +85C) | [DATA_NEEDED: commercial/industrial temperature grade] |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| User I/O | — | 149 |
| Propagation Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Pin/Package Code | — | TC208 (JEDEC S-PQFP-G208) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Technology | — | CMOS EEPROM |
| Core Supply Voltage | — | 5 V |
| I/O Supply Voltage (MultiVolt) | — | 3.3 V or 5 V |
| In-System Programming | — | Yes (IEEE Std 1149.1 JTAG) |
| Flip-Flops | — | 772 |