EPM9560WC208-15 vs EPM9560RC208-15N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560WC208-15 sa pamamagitan ng Altera at EPM9560RC208-15N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EPM9560RC208-15N EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9560WC208-15 EPM9560RC208-15N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 9000 —
Device Type EE PLD (Electrically Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Technology CMOS —
Macrocells 560 560
Logic Array Blocks (LABs) 35 16
Flip-Flops 772 —
User I/O Pins (max) 149 —
Maksimum na Taktiko ng Oras 117.6 MHz —
Propagation Delay (tPD) 16.6 ns —
Speed Grade -15 -15 (15 ns tPD)
Supply Voltage - I/O 3.3 V or 5.0 V (configurable) —
Packhaging 208-pin CQFP (Ceramic Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Terminal Pitch 0.50 mm —
Uri ng Pagpapasok Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1 boundary scan) —
Tindminan RoHS RoHS3 Compliant (per third-party listings) [DATA_NEEDED: check part marking suffix for lead-free/RoHS]
Series — MAX 9000
Usable Gates — 12,000
User I/O — 212 (in 208-RQFP, see family datasheet)
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Internal Frequency — 117.6 MHz
Supply Voltage (VCCINT) — 5.0 V
Programmability — In-system via IEEE 1149.1 JTAG
Configuration Memory — CMOS EEPROM (non-volatile)
Operating Temperature (commercial) — 0C to +70C
Architecture — Multiple Array MatriX (MAX) - third generation

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