K3KL3L30CM-BGCT vs K3LKBKB0BM-MGCP Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng K3KL3L30CM-BGCT sa pamamagitan ng Samsung Electronics at K3LKBKB0BM-MGCP sa pamamagitan ng Samsung Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Samsung Electronics
K3LKBKB0BM-MGCP - 32Gbit LPDDR5 DRAM 6400Mbps | Samsung
K3LKBKB0BM-MGCP ✓ NakahandaPagsanggunian na paghahambing
| Parametro | K3KL3L30CM-BGCT | K3LKBKB0BM-MGCP |
|---|---|---|
| Brand | Samsung Electronics | Samsung Electronics |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Presyo ng Yunit (USD) | — | $46.62 |
| Uri ng Memory | LPDDR5X SDRAM | DRAM (LPDDR5 SDRAM) |
| Density | 64 Gbit | — |
| Organisasyon | x64 | 1G x 32 |
| Speed Grade | LPDDR5X-7500 (7500 MT/s) | — |
| Technology | Stacked DRAM die, mobile BGA | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Packhaging | [DATA_NEEDED: exact package code and ball count] | FBGA-315 |
| Core Voltage | [DATA_NEEDED: VDD core voltage] | — |
| I/O Voltage (VDDQ) | [DATA_NEEDED: VDDQ voltage] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -25C to +85C |
| Refresh | [DATA_NEEDED: refresh scheme] | Self-refresh and auto-refresh (LPDDR5 standard) |
| Standards Compliance | JEDEC LPDDR5X specification | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Application Class | Mobile / embedded main memory | — |
| Laki ng Memory | — | 32 Gbit |
| Rate ng Data | — | 6400 Mbps per pin |
| Supply Voltage Rails | — | 500 mV, 900 mV, 1.05 V, 1.8 V |
| Interface | — | LPDDR5 x32 |
| Technology Generation | — | LPDDR5 (JEDEC LPDDR5 family) |
| Density per Package | — | 4 GB (32 Gbit) |
| Application Segment | — | Mobile, embedded, industrial computing |
| Standby / Deep Sleep | — | LPDDR5 deep-sleep power states |
| Access Time / Latency | — | [DATA_NEEDED: CAS latency] |