LFE2-20E-5F484C vs LFE2-6E-5F256I Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng LFE2-20E-5F484C sa pamamagitan ng Lattice Semiconductor at LFE2-6E-5F256I sa pamamagitan ng Lattice Semiconductor. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Lattice Semiconductor
LFE2-6E-5F256I - 6K LUT, 190 I/O ECP2 FPGA | Lattice
LFE2-6E-5F256I ✓ NakahandaPagsanggunian na paghahambing
| Parametro | LFE2-20E-5F484C | LFE2-6E-5F256I |
|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Unknown | Aktibo |
| Device Type | ECP2 Field Programmable Gate Array (FPGA) | ECP2 Field Programmable Gate Array (FPGA) |
| Logic Cell Density | 21K LUTs | — |
| Input/Output Count | 331 I/O | — |
| Core Supply Voltage | 1.2 V | — |
| Speed Grade | -5 | -5 |
| DSP Capability | DSP | — |
| Packhaging | 484-BBGA | 256-ball Fine Pitch Ball Grid Array |
| Package Type | BGA | — |
| Terminal Count | 484 balls | 256 balls |
| Uri ng Pagpapasok | Surface Mount | Surface mount |
| Programmable Device | Yes | — |
| FPGA Family | LatticeECP2 | — |
| Logic Technology | 90 nm CMOS | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| Maksimum na Taktiko ng Oras | [DATA_NEEDED: maximum clock frequency] | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| Logic Cells | — | 6,000 cells |
| User I/O | — | 190 I/O |
| Configuration Bits | — | 56,320 bits |
| Core Supply | — | 1.2 V |
| Temperature Grade | — | Industrial |
| Package Abbreviation | — | FPBGA-256 |
| Package Dimensions | — | 17 mm x 17 mm |
| Package Shape | — | Square |
| Terminal Type | — | Ball |
| Lead-Free Status | — | Lead free |
| Programmable Logic Type | — | FPGA |
| DSP Support | — | Advanced DSP blocks supported by the LatticeECP2/M family |
| SERDES Support | — | High-speed SERDES supported by the LatticeECP2M family |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification status] |