MPC8533EVTAQGA vs MPC8536EAVTAQG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng MPC8533EVTAQGA sa pamamagitan ng NXP Semiconductors at MPC8536EAVTAQG sa pamamagitan ng NXP Semiconductors. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
NXP Semiconductors
MPC8533EVTAQGA - PowerQUICC III 1GHz SoC, 783-FCBGA | NXP
MPC8533EVTAQGA ✓ NakahandaNXP Semiconductors
MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale
MPC8536EAVTAQG NrndPagsanggunian na paghahambing
| Parametro | MPC8533EVTAQGA | MPC8536EAVTAQG |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | PowerQUICC III | — |
| Core Architecture | PowerPC e500v2 | — |
| Core Count | 1 | — |
| Width ng Data Bus | 32-bit | 32 bit |
| Maximum Core Frequency | 1.0 GHz | — |
| L1 Cache | 32 KB I-cache + 32 KB D-cache | — |
| L2 Cache | 256 KB (per core, on-chip) | — |
| Memory Controller | DDR1/DDR2 with ECC | — |
| Ethernet | 3x 10/100/1000 Mb/s MAC (1 GbE) | — |
| PCI Express | 2x PCIe interfaces | — |
| PCI | 1x PCI 32-bit/66 MHz | — |
| USB | USB 2.0 (host/device) | — |
| Security Engine | SEC 2.0 (IPSec/SSL/SRTP) | — |
| Temperature na Operasyon | 0C to +90C (commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | 783-FCPBGA (29x29 mm) | 783-FCPBGA (29x29 mm) |
| Silicon Revision | Rev 2.1 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Processor Series | — | MPC85xx (PowerQUICC III) |
| Core | — | PowerPC e500, 32-bit |
| Maksimum na Taktiko ng Oras | — | 1.0 GHz |
| Number of Cores | — | 1 |
| Encryption Support | — | Yes ('E' suffix indicates encryption-enabled silicon) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: core/IO supply voltage] |
| Integrated Peripherals | — | QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express |
| Instruction Set Architecture | — | Power Architecture (Book-E) |
| On-chip Cache | — | [DATA_NEEDED: L1/L2 cache configuration] |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |