SY58052AUMG-TR vs SY58052AUMG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng SY58052AUMG-TR sa pamamagitan ng Microchip Technology at SY58052AUMG sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
SY58052AUMG-TR - 10.7Gbps CML Data-Clock Synchronizer | Microchip
SY58052AUMG-TR ✓ NakahandaMicrochip Technology
SY58052AUMG - 10.7Gbps CML Clock Synchronizer | Microchip
SY58052AUMG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | SY58052AUMG-TR | SY58052AUMG |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | Clock & Timing | Clock & Timing |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Fungsi | Ultra-precision CML data and clock synchronizer (retimer) | Ultra-precision CML data and clock synchronizer (resynchronizer) |
| Maximum Data Rate | 10.7 Gbps | — |
| Maksimum na Taktiko ng Oras | 10.7 GHz | — |
| Input Type | Differential CML with internal termination (VT pin) | — |
| Type ng Output | Differential CML | CML |
| Supply Voltage Range | 2.375 V to 3.63 V | 2.375 V to 3.63 V |
| Temperature na Operasyon | -40C to +85C | -40C to +85C |
| Packhaging | 16-VFQFN (3x3 mm) Exposed Pad | 16-VFQFN exposed pad (3x3 mm) |
| Number of Channels | 1 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Coupling Support | AC-coupled and DC-coupled interfaces | — |
| Termination | Internal input and output termination | — |
| Applications Category | ATM/SONET/SDH support circuit | — |
| Terminal Form | No lead | — |
| Package Code | HVQCCN (square) | — |
| Temperature Grade | Industrial | — |
| Maximum Data Throughput | — | > 10.7 Gbps |
| Maximum Clock Frequency (fMAX) | — | > 10.7 GHz |
| Any Input to Any Output Delay | — | 160 ps max |
| Input Types | — | CML, PECL, data inputs |
| Product Family | — | Precision Edge(R) |
| Internal Termination | — | Input and output termination integrated |
| Primary Application | — | Backplane retiming / data-to-clock resynchronization |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS Status] |
| Level ng MSL | — | [DATA_NEEDED: MSL Level] |