XC3090L-8PCG84C vs XC3090L-125PC84C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng XC3090L-8PCG84C sa pamamagitan ng Xilinx at XC3090L-125PC84C sa pamamagitan ng Xilinx. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | XC3090L-8PCG84C | XC3090L-125PC84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | XC3000A/L Series FPGA | — |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | — |
| Packhaging | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (J-lead, package code QCCJ) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | 3.0 V to 3.6 V (typical 3.3 V) |
| Speed Grade | -8 (moderate) | — |
| Temperature na Operasyon | 0 C to +70 C (commercial 'C' suffix) | Commercial (0C to +70C) - exact grade [DATA_NEEDED: temperature grade] |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | CMOS, SRAM-based |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Uri ng Pagpapasok | Surface Mount (PLCC J-Lead) | Surface Mount |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | unknown | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Manufacturer | — | Xilinx |
| Series | — | XC3000L |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Logic Family | — | XC3000L Low-Voltage Logic Cell Array |
| Configurable Logic Blocks (CLBs) | — | 320 |
| Equivalent Gates | — | ~5,000 |
| Flip-Flops | — | 928 |
| Maximum Toggle Frequency | — | 125 MHz |
| Terminal Form | — | J-BEND (J-lead) |
| Configuration Interface | — | Serial/parallel mode, JTAG (IEEE 1149.1) |