EP1810LI-25 vs EP1810LI-35 Karşılaştırma

Ayrıntılı yan yana karşılaştırma EP1810LI-25 tarafından Altera ve EP1810LI-35 tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre EP1810LI-25 EP1810LI-35
Marka Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Yaşam Döngüsü Durumu Obsolete Obsolete
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device), UV-erasable / OTP Erasable Programmable Logic Device (EPLD)
Macrocells 48 48
Usable Gates 900 —
Propagation Delay (tPD) 25 ns 35 ns
Maximum Counter Frequency 40 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
I/O Pins 48 —
Dedicated Inputs 12 —
Global Clock Inputs 4 —
Interconnect Programmable global and local buses —
Paket 68-pin PLCC (J68, J-Lead) 68-pin PLCC (J-Lead, plastic)
JESD-30 Package Code S-PQCC-J68 —
Process Technology CMOS —
Operating Temperature (Industrial 'I' suffix) -40 C to +85 C —
Programming Mode EPROM/UV-erasable (windowed) and OTP —
Development Tool Altera MAX+PLUS II —
RoHS Durumu unknown [DATA_NEEDED: RoHS compliance status]
Lead-Free Status unknown —
Manufacturer — Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Speed Grade — 35 (slowest in EP1810L family)
Pin/Package Code — PLCC-68 / PQCC68
Technology — CMOS, UV-erasable EPROM configuration cell
Besleme Gerilimi — 5 V (TTL-compatible I/O)
İşletim Sıcaklığı — -40 C to +85 C (industrial, 'I' suffix)
Montaj Türü — Surface Mount (PLCC socket compatible)
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Lead-Free — [DATA_NEEDED: lead-free status]
MSL Seviyesi — [DATA_NEEDED: MSL rating]

Dökümanlar & Kaynaklar

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