AD9235BRURL7-65 - 12-Bit 65 MSPS ADC, 3V, TSSOP-28 | Analog Devices
MPN: AD9235BRURL7-65 ✓ Hoạt độngAD9235BRURL7-65 Tóm tắt
An ADC (analog-to-digital converter) is a semiconductor device that converts a continuous analog voltage into a discrete digital code at a sampling rate set by an external clock. Pipelined ADCs like the AD9235 use a multi-stage architecture that enables high sample rates at low power, while 12-bit resolution is the workhorse for cellular base stations, ultrasound imaging, and instrumentation. Within the broader taxonomy, the AD9235 sits in the data-converter category of mixed-signal ICs.
Key features of the AD9235BRURL7-65 include a differential analog input with 500 MHz bandwidth, an on-chip sample-and-hold amplifier (SHA), an internal voltage reference, and ±0.4 LSB differential non-linearity (DNL). The analog input range scales from 1 V p-p to 2 V p-p, output data is available in offset-binary or twos-complement format, and an integrated clock-duty-cycle stabilizer (DCS) relaxes clock-source requirements.
A proprietary front-end SHA driving the pipelined core allows IF-sampling well beyond the Nyquist limit, useful in undersampling radio receivers. Power consumption is 300 mW at 65 MSPS, and a flexible LVCMOS/TTL-compatible parallel digital interface simplifies FPGA/CPLD downstream connections.
Typical applications include communications IF sampling, ultrasound and medical imaging front-ends, low-cost instrumentation, and high-speed data acquisition cards. Designers value the part when a low-power, single-supply 12-bit ADC in a compact surface-mount footprint is needed.
When laying out the PCB, keep analog and digital grounds separated and join them at a single point near the ADC to limit return-path noise; place the input anti-alias filter as close as practical to the analog inputs and use a stable, low-jitter clock source to preserve SNR and SFDR.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and PCB-level design notes not found in the manufacturer datasheet, helping engineers select the right speed grade and validate second-source supply.
Bộ thay thế dễ dàng lắp đặt cho AD9235BRURL7-65 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với AD9235BRURL7-65 (cùng hình factor và footprint) — khác nhau ở Reference, Supply Voltage.
AD9235BRUZRL7-65
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9235BRU-65
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9235BRURL7-40
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →AD9235BRU-20
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
AD9236BRUZ-80
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
AD9235BRURL7-65 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bits |
| Number of Channels | 1 |
| Sampling Rate (Max) | 65 MSPS |
| Architecture | Pipelined |
| Điện áp cung cấp | 3 V (2.7 V to 3.6 V) |
| Power Consumption | 300 mW at 65 MSPS |
| Analog Input Bandwidth | 500 MHz |
| Analog Input Range | 1 V p-p to 2 V p-p |
| Analog Input Type | Differential |
| SNR (to Nyquist, -1 dBFS) | 70 dBFS |
| SFDR (to Nyquist) | 85 dBFS |
| DNL | +/-0.4 LSB (typical) |
| Data Interface | Parallel (LVCMOS/TTL) |
| Output Format | Offset binary or twos complement |
| Reference | Internal (on-chip) |
| Clock Duty-Cycle Stabilizer | Yes (integrated) |
| Khoảng nhiệt độ hoạt động | -40C to +85C |
| Hộp | 28-TSSOP (4.40 mm body width) |
| Kiểu lắp đặt | Surface Mount |
| Cấp MSL | 1 (unlimited floor life) |
Cấu hình chân AD9235BRURL7-65
| Chân 1 | DVDD — Digital supply voltage (3 V) |
| Chân 2 | DGND — Digital ground |
| Chân 3 | CLOCK+ — Differential clock input, positive |
| Chân 4 | CLOCK- — Differential clock input, negative |
| Chân 5 | AIN- — Differential analog input, negative |
| Chân 6 | AIN+ — Differential analog input, positive |
| Chân 7 | VREF — Internal reference bypass / external reference input |
| Chân 8 | REFT — Internal reference top decoupling |
| Chân 9 | REFB — Internal reference bottom decoupling |
| Chân 10 | AVDD — Analog supply voltage (3 V) |
| Chân 11 | AGND — Analog ground |
| Chân 12 | CML — Common-mode level bypass (drive bias for analog inputs) |
| Chân 13 | AVDD2 — Analog supply (input buffer) |
| Chân 14 | AGND2 — Analog ground (input buffer) |
| Chân 15 | D11 (MSB) — Parallel data output, MSB |
| Chân 16 | D10 — Parallel data output |
| Chân 17 | D9 — Parallel data output |
| Chân 18 | D8 — Parallel data output |
| Chân 19 | D7 — Parallel data output |
| Chân 20 | D6 — Parallel data output |
| Chân 21 | D5 — Parallel data output |
| Chân 22 | D4 — Parallel data output |
| Chân 23 | D3 — Parallel data output |
| Chân 24 | D2 — Parallel data output |
| Chân 25 | D1 — Parallel data output |
| Chân 26 | D0 (LSB) — Parallel data output, LSB |
| Chân 27 | OTR — Out-of-range flag |
| Chân 28 | DCS/PD — Clock-duty-cycle stabilizer or power-down control |
Ứng dụng tiêu biểu
AD9235BRURL7-65 phù hợp cho 6 Áp dụngs: Communications IF Sampling Receiver, Medical Ultrasound Imaging Front-End, Portable Instrumentation and Data Acquisition, Low-Cost Multichannel Wireless Receiver, Industrial Process Control Measurement, Time-Interleaved or Multi-Board Baseband Recorder.
Communications IF Sampling Receiver
The AD9235BRURL7-65 is used in IF stages of cellular base-station receivers and microwave-link down-converters where the ADC samples a low-IF or zero-IF modulated carrier. Its 500 MHz analog input bandwidth and 65 MSPS sampling clock comfortably support IFs in the 25-100 MHz range, while the 70 dBFS SNR to Nyquist gives the back-end DSP >11 ENOB at oversampled baseband. Combined with a 3 V single supply and 300 mW dissipation, it cuts thermal load versus legacy 5 V ADCs, and the integrated clock-duty-cycle stabilizer relaxes jitter margin on TCXO-derived clocks.
Được đề xuất
Medical Ultrasound Imaging Front-End
In ultrasound beamformers the AD9235BRURL7-65 digitizes the receive channel after TGC and LNA stages. The 12-bit resolution at 65 MSPS captures the dynamic range of returning echoes from deep tissue while keeping the LVCMOS parallel interface compatible with mid-range FPGAs. Its 300 mW dissipation lets designers stack 16-32 channels on a single board without exceeding thermal budgets. The integrated SHA and differential front-end reject common-mode pickup from piezo cables.
Được đề xuất
Portable Instrumentation and Data Acquisition
Hand-held oscilloscope and field data-acquisition cards adopt the AD9235BRURL7-65 to deliver 12-bit precision at 65 MSPS on a single 3 V rail, ideal for battery-powered applications. The parallel output bus feeds directly into an FPGA or Cortex-M4-based MCU with DMA, while 1 V p-p to 2 V p-p range supports both legacy and modern sensor outputs. Low 300 mW dissipation enables fan-less mechanical designs suitable for IP-rated enclosures.
Được đề xuất
Low-Cost Multichannel Wireless Receiver
Cost-sensitive wireless LNBs and broadband software-defined-radio dongles use the AD9235BRURL7-65 as the digital IF digitizer. Its 12-bit accuracy at 65 MSPS provides headroom for narrowband digital filtering, while the 28-TSSOP footprint enables dense PCB layouts behind multi-element antenna arrays. Internal reference removes external precision components, and the optional twos-complement output simplifies signed-math DSP pipelines.
Được đề xuất
Industrial Process Control Measurement
Distributed control systems (DCS) and condition-monitoring vibration sensors use the AD9235BRURL7-65 to capture vibration and acoustic-emission waveforms in rotating machinery. Its 70 dBFS SNR preserves harmonic detail for FFT-based diagnostics, while the industrial -40C to +85C operating range matches factory-floor requirements. Single-supply 3 V simplifies integration into PLC modules powered from 24 V via a small point-of-load regulator.
Được đề xuất
Time-Interleaved or Multi-Board Baseband Recorder
Multi-board data-acquisition chassis interleave multiple AD9235BRURL7-65 ADCs to reach sample rates from 130 MSPS to several hundred MSPS for radar baseband recorders and high-throughput test instruments. The closely matched analog front-end preserves channel-to-channel gain and offset alignment, while the wide 500 MHz input bandwidth eases design-in of anti-alias filtering. Synchronized via a shared low-jitter clock, the parallel outputs multiplex cleanly into high-density FPGAs.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho AD9235BRURL7-65 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | AD9235BRUZRL7-65 | AD9235BRU-65 | AD9235BRURL7-40 | AD9235BRU-20 | AD9236BRUZ-80 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-TSSOP (BRURL7) | 28-TSSOP - same | 28-TSSOP - same | 28-TSSOP - same | 28-TSSOP - same | 28-TSSOP - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Max Sample Rate | 65 MSPS | 65 MSPS | 65 MSPS | 40 MSPS (-38%) | 20 MSPS (-69%) | 80 MSPS (+23%) |
| Supply Voltage | 3 V (2.7-3.6 V) | 3 V | 3 V | 3 V | 3 V | 3 V |
| Lead Finish (RoHS) | SnPb (legacy) | Pb-free / RoHS | SnPb (legacy) | SnPb (legacy) | SnPb (legacy) | Pb-free / RoHS |
| Packaging Form | Tape & Reel (7") | Tape & Reel (7") | Tube | Tape & Reel (7") | Tube | Tube |
| Pin Count | 28 | 28 | 28 | 28 | 28 | 28 |
Bảo phân biệt quan trọng
- Single 3 V analog supply, no negative rail needed (vsAD9235BRU-20)
- Integrated clock duty-cycle stabilizer (vsAD9235BRURL7-40)
- 500 MHz analog input bandwidth enables IF undersampling (vsAD9235BRU-65 (tube))
Ghi chú thiết kế
Estimated: at 65 MSPS and a single 3.0 V supply the AD9235BRURL7-65 draws ~100 mA (300 mW / 3 V). Apply a 10 uF + 0.1 uF local capacitor pair on each of AVDD, AVDD2, and DVDD - placed within 3 mm of their respective pins - to suppress switching-cell transient currents from coupling back through the supply. Use a ferrite bead between the analog and digital rails and join the grounds at a single-point star under the exposed pad or pin 11/14 region.
Estimated: route the differential analog inputs AIN+/AIN- as 50 ohm microstrip or stripline of matched length (delta <0.5 mm) and keep them away from digital output traces - digital switching noise couples easily into the SHA. The differential clock traces CLK+/CLK- should follow the same matched-length discipline. Reference the AVDD/AVDD2 returns directly to the analog ground plane, not the digital ground plane, and place the CML pin bypass cap directly at pin 12.
Avoid single-ended clock or analog-input drive - the AD9235's SHA is engineered for fully differential operation and the SNR/SFDR will degrade 10-20 dB with single-ended signals. Activate the clock-duty-cycle stabilizer (DCS) by tying pin 28 (DCS/PD) low via a 1 k resistor, or float it; tying it high puts the part into power-down. Decouple REFT and REFB at pins 8-9 with 10 uF + 0.1 uF ceramic across each; do not apply external load currents to these reference pins.
Estimated: total throughput SNR including jitter is SNR_total = -10*log10[(2*pi*f_in*t_j)^2 + (1/SNR_ADC)]; a 65 MSPS ADC and a 70 MHz IF require <2 ps RMS clock jitter to stay within 1 dB of the datasheet's 70 dBFS floor. Use a low-jitter TCXO or a clock-distribution IC such as AD9516 and confirm jitter-budget with a phase-noise analyzer before locking down the design.
Thông tin tuân thủ
RL7 (non-Z) order code uses legacy lead-containing finish per Analog Devices naming convention; new designs should select the Z-suffix RoHS variant. AEC-Q100 not applicable for industrial/consumer ADC. REACH / halogen / conflict-mineral status not stated in retrieved datasheet preview.
