ADC12DL040CIVS - Dual 12-Bit 40 MSPS 3V ADC | Texas Instruments
MPN: ADC12DL040CIVS ✗ Cuối đờiADC12DL040CIVS Tóm tắt
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes input samples through a cascade of low-resolution flash stages with inter-stage digital error correction. Pipelined ADCs occupy the middle ground between flash converters (highest speed, highest power) and successive-approximation register (SAR) ADCs (lower speed, lower power), making them the dominant architecture for communications baseband, IF sampling, CCD imaging, and multi-channel data acquisition where tens of MSPS at 8-14 bits are required. The ADC12DL040CIVS sits firmly in this niche as a dual-channel, 12-bit, 40 MSPS converter.
Key features include 69 dB typical SNR at fIN = 10 MHz, 85 dB typical SFDR at fIN = 10 MHz, ±0.3 LSB typical DNL, 2.4 V to 3.6 V digital output driver supply for flexible interfacing to lower-voltage FPGAs/ASICs, a duty cycle stabilizer for robust performance with non-50% clock duty cycles, a power-down mode, and a multiplexed output mode that places both channels on a single 12-bit bus. Industrial temperature range operation spans -40 °C to +85 °C.
The ADC12DL040 uses a switched-capacitor pipelined architecture with proprietary digital correction logic. Each channel contains an input sample-and-hold amplifier, a switched-capacitor multiplying-DAC front end, and successive flash stages producing 12-bit latency-corrected outputs. The internal precision reference is trimmed at the factory and is not user-adjustable, simplifying PCB layout while ensuring channel-to-channel gain matching within ±0.5 %.
Typical applications include IF/baseband sampling in communications receivers, dual-channel CCD imaging digitizers, medical ultrasound beamformers, portable test and measurement instruments, and multi-axis industrial data acquisition systems. The dual-channel integration halves board area versus two discrete single-channel ADCs and guarantees matched AC performance between channels.
When designing with this part, drive the analog inputs with a low-impedance op-amp buffer (such as the THS4631 or LMH6624) to avoid sample-and-hold distortion. The 50 Ω clock input is critical: drive it from a low-jitter source (sub-ps RMS) to maximize SNR at high input frequencies. Decouple AVDD and DVDD separately with 0.1 µF ceramic + 10 µF tantalum capacitors placed within 5 mm of each supply pin.
This page synthesizes distributor pricing, drop-in alternatives within the 64-pin TQFP footprint, and practical design notes not found in the manufacturer datasheet alone.
Bộ thay thế dễ dàng lắp đặt cho ADC12DL040CIVS — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADC12DL040CIVS (cùng hình factor và footprint) — khác nhau ở Number of Channels, Architecture, Resolution, Analog Supply Voltage, Package.
ADC12DL040CIVS/NOPB
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADC12DL065CIVS/NOPB
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADC12040CIVY
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ADC10D020CIVSX/NOPB
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC12DL040CIVS Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 Bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate (per channel) | 40 MSPS |
| Architecture | Pipelined CMOS |
| Analog Supply Voltage | 3.0 V (2.7 V to 3.6 V range) |
| Digital Output Driver Supply | 2.4 V to 3.6 V (separate DVDD) |
| Power Dissipation (typical) | 210 mW |
| Power-Down Mode | Yes |
| SNR (fIN = 10 MHz) | 69 dB (typical) |
| SFDR (fIN = 10 MHz) | 85 dB (typical) |
| DNL (Differential Non-Linearity) | ±0.3 LSB (typical) |
| Internal Reference | Yes (factory-trimmed, not user-adjustable) |
| Sample-and-Hold | Internal, dual |
| Duty Cycle Stabilizer | Yes |
| Multiplexed Output Mode | Yes (channels share single 12-bit bus) |
| Output Format | Straight Binary, offset binary, 2's complement (per pin strapping) |
| Input Clock | Single-ended or differential; 50 Ω terminated internally |
| Nhiệt độ hoạt động | -40 °C to +85 °C (industrial) |
| Hộp | 64-pin TQFP (PAG) 10x10 mm, surface-mount |
| Lead Finish / RoHS | Lead-free / RoHS status depends on orderable suffix (see datasheet ordering info) |
Cấu hình chân ADC12DL040CIVS
| Chân 1 | VINA — Analog input channel A positive |
| Chân 2 | VINA- — Analog input channel A negative (complementary) |
| Chân 3 | AGND — Analog ground |
| Chân 4 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 5 | VREF — Internal reference bypass / external reference input |
| Chân 6 | AGND — Analog ground |
| Chân 7 | VINB — Analog input channel B positive |
| Chân 8 | VINB- — Analog input channel B negative (complementary) |
| Chân 9 | AGND — Analog ground |
| Chân 10 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 11 | CLK_A — Channel A clock input (positive) |
| Chân 12 | CLK_A- — Channel A clock input (negative) |
| Chân 13 | AGND — Analog ground |
| Chân 14 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 15 | PD — Power-down control (active high) |
| Chân 16 | DCS — Duty cycle stabilizer enable |
| Chân 17 | MUX — Multiplexed output mode enable |
| Chân 18 | DGND — Digital ground |
| Chân 19 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| Chân 20 | D0_A — Channel A data bit 0 (LSB) |
| Chân 21 | D1_A — Channel A data bit 1 |
| Chân 22 | D2_A — Channel A data bit 2 |
| Chân 23 | D3_A — Channel A data bit 3 |
| Chân 24 | D4_A — Channel A data bit 4 |
| Chân 25 | D5_A — Channel A data bit 5 |
| Chân 26 | D6_A — Channel A data bit 6 |
| Chân 27 | D7_A — Channel A data bit 7 |
| Chân 28 | D8_A — Channel A data bit 8 |
| Chân 29 | D9_A — Channel A data bit 9 |
| Chân 30 | D10_A — Channel A data bit 10 |
| Chân 31 | D11_A — Channel A data bit 11 (MSB) |
| Chân 32 | DGND — Digital ground |
| Chân 33 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| Chân 34 | D0_B — Channel B data bit 0 (LSB) |
| Chân 35 | D1_B — Channel B data bit 1 |
| Chân 36 | D2_B — Channel B data bit 2 |
| Chân 37 | D3_B — Channel B data bit 3 |
| Chân 38 | D4_B — Channel B data bit 4 |
| Chân 39 | D5_B — Channel B data bit 5 |
| Chân 40 | D6_B — Channel B data bit 6 |
| Chân 41 | D7_B — Channel B data bit 7 |
| Chân 42 | D8_B — Channel B data bit 8 |
| Chân 43 | D9_B — Channel B data bit 9 |
| Chân 44 | D10_B — Channel B data bit 10 |
| Chân 45 | D11_B — Channel B data bit 11 (MSB) |
| Chân 46 | DGND — Digital ground |
| Chân 47 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| Chân 48 | OFR_A — Channel A out-of-range indicator |
| Chân 49 | OFR_B — Channel B out-of-range indicator |
| Chân 50 | DGND — Digital ground |
| Chân 51 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| Chân 52 | NC — Not connected (per datasheet) |
| Chân 53 | NC — Not connected (per datasheet) |
| Chân 54 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 55 | AGND — Analog ground |
| Chân 56 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 57 | NC — Not connected (per datasheet) |
| Chân 58 | NC — Not connected (per datasheet) |
| Chân 59 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 60 | AGND — Analog ground |
| Chân 61 | AVDD — Analog supply (+3.0 V nominal) |
| Chân 62 | NC — Not connected (per datasheet) |
| Chân 63 | NC — Not connected (per datasheet) |
| Chân 64 | AVDD — Analog supply (+3.0 V nominal) |
Ứng dụng tiêu biểu
ADC12DL040CIVS phù hợp cho 6 Áp dụngs: Communications IF / Baseband Sampling, Medical Ultrasound Beamformer Front-End, Dual-Channel CCD / CMOS Image Digitizer, Portable Test & Measurement Instrumentation, Multi-Axis Industrial Data Acquisition, Radar / Lidar Baseband Digitization.
Communications IF / Baseband Sampling
The ADC12DL040CIVS suits IF and baseband sampling in software-defined radio receivers and broadband communications base stations. With 40 MSPS per channel and 69 dB SNR at fIN = 10 MHz, two independent channels can simultaneously digitize I/Q baseband or a single IF chain, halving board area versus two discrete single-channel ADCs. The 2.4-3.6 V separate digital output supply lets the ADC12DL040CIVS drive a 2.5 V FPGA logic bank without level shifters, simplifying PCB layout and reducing BOM cost in compact SDR modules.
Được đề xuất
Medical Ultrasound Beamformer Front-End
The dual 12-bit 40 MSPS channels of the ADC12DL040CIVS are widely deployed in medical ultrasound beamformer front-ends. Each ADC12DL040CIVS handles two adjacent transducer elements simultaneously, with channel-to-channel gain matching enforced by the internal factory-trimmed reference. At 5-15 MHz ultrasound frequencies, 40 MSPS comfortably exceeds the Nyquist requirement, and 85 dB SFDR preserves harmonics-free echo signals. Multiple ADC12DL040CIVS parts are typically clocked from a single low-jitter PLL for phase-coherent array acquisition.
Được đề xuất
Dual-Channel CCD / CMOS Image Digitizer
The ADC12DL040CIVS digitizes dual CCD or CMOS image sensor analog outputs in industrial and scientific cameras. The dual channel simultaneous sampling preserves pixel-by-pixel correlation between two sensor regions, while 12-bit resolution captures the dynamic range needed for color and low-light imaging. 210 mW typical power keeps thermal dissipation manageable in enclosed camera housings, and the integrated sample-and-hold eliminates the need for external track-and-hold amplifiers on each channel.
Được đề xuất
Portable Test & Measurement Instrumentation
For handheld oscilloscopes, spectrum analyzers, and data loggers, the ADC12DL040CIVS delivers 12-bit resolution at 40 MSPS in a small 10x10 mm TQFP footprint. The single 3.0 V analog supply plus 2.4-3.6 V digital supply simplifies battery-powered designs, while 210 mW power dissipation keeps the device within portable instrument thermal budgets. The multiplexed output mode can route both channels through one 12-bit bus, reducing FPGA pin count in cost-sensitive instruments.
Được đề xuất
Multi-Axis Industrial Data Acquisition
The ADC12DL040CIVS handles multi-axis vibration, strain gauge, and pressure transducer digitizers in industrial predictive-maintenance systems. Each part captures two sensor channels simultaneously, and stacking multiple ADC12DL040CIVS ICs in parallel expands channel count while sharing one low-jitter clock. The industrial -40 °C to +85 °C temperature range supports deployment in factory-floor enclosures, and the duty cycle stabilizer tolerates non-50% clock duty cycles common in industrial backplanes.
Được đề xuất
Radar / Lidar Baseband Digitization
The ADC12DL040CIVS serves as the baseband digitizer in short-range automotive radar, security radar, and lidar receiver chains. With two simultaneous sampling channels and 69 dB SNR at 10 MHz, the device cleanly captures I/Q radar baseband returns from down-converted IF stages. The internal reference reduces external component count, which is critical for the small form factor of automotive-grade sensor modules. The TQFP-64 footprint also eases hand-rework during prototyping of radar front-ends.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADC12DL040CIVS — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADC12DL040CIVS/NOPB | ADC12DL065CIVS/NOPB | ADC12040CIVY | ADC10D020CIVSX/NOPB |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-pin TQFP (PAG) 10x10 mm | 64-pin TQFP (PAG) 10x10 mm - same | 64-pin TQFP (PAG) 10x10 mm - same | 64-pin TQFP (PAG) 10x10 mm - same | 64-pin TQFP (PAG) 10x10 mm - same |
| Resolution | 12 Bits | 12 Bits | 12 Bits | 12 Bits | 10 Bits |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 2 (dual) |
| Sample Rate (per channel) | 40 MSPS | 40 MSPS | 65 MSPS (+62.5%) | 40 MSPS | 20 MSPS (-50%) |
| Supply Voltage (Analog) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
Bảo phân biệt quan trọng
- Identical die with lead-free RoHS finish (vsADC12DL040CIVS/NOPB)
- Higher sample rate in identical package (vsADC12DL065CIVS/NOPB)
- Single-channel option for cost-down designs (vsADC12040CIVY)
Ghi chú thiết kế
Estimated: separate the analog (AVDD) and digital (DRVDD) power planes, and join them at a single point near the AGND/DGND pin junction. Place 0.1 µF ceramic + 10 µF tantalum decoupling pairs on every AVDD and DRVDD pin, within 5 mm of the IC. The analog inputs are sensitive to ground bounce, so route VIN± over a continuous ground plane and avoid crossing digital output traces on adjacent layers.
The CLK± pins require a low-jitter differential clock source; SNR degrades by 20·log10(1/(2π·fIN·t_jitter)) dB for a given input frequency. For 69 dB SNR at 10 MHz fIN, the clock RMS jitter must be below ~2 ps. Drive the CLK± pins through a 1:1 RF transformer (such as Mini-Circuits ADT1-1WT) from a clean oscillator or PLL output. Keep clock traces short, length-matched, and routed over a continuous ground plane.
Do not float the PD (power-down) pin — tie it low via a 10 kΩ resistor for normal operation. Leave the DCS (duty cycle stabilizer) pin enabled unless the source clock already has < 1 % duty-cycle error; disabling DCS with a non-50 % clock degrades SNR. For maximum SFDR, drive the analog inputs with a low-distortion, low-impedance op-amp such as the THS4631; passive RC networks alone are insufficient at IF frequencies.
Estimated: with 210 mW dissipation in a 64-pin TQFP (θJA ≈ 60 °C/W on a 4-layer JEDEC board), the junction temperature rise is approximately 12.6 °C above ambient, well within the 125 °C absolute maximum. If the ADC is deployed alongside other heat-dissipating components in a sealed enclosure, verify with thermal imaging under worst-case ambient. The exposed thermal pad is not present on this TQFP package, so all heat exits through the leads and PCB copper pour.
Route channel-A and channel-B analog input traces symmetrically, with matched length and identical via counts, to preserve channel-to-channel gain and phase matching. Place the input anti-aliasing RC network (typically 50 Ω + 10 pF) within 5 mm of each VIN± pin. Use a guard trace tied to analog ground around the input pair to reject digital noise coupling from the parallel data-bus traces below.
Thông tin tuân thủ
RoHS/REACH/AEC-Q100 status not explicitly present in the verified web data; refer to the TI product page ordering table for the specific finish of the suffix shipped. Standard lead-free / NOPB variants are typically RoHS compliant; the bare CIVS suffix without /NOPB is generally the non-RoHS (lead-bearing) finish.
