ADC12DL040CIVS - Dual 12-Bit 40 MSPS 3V ADC | Texas Instruments
부품 번호: ADC12DL040CIVS ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.75 | $167.50 |
| 100 | $14.92 | $1,492.00 |
| 500 | $13.3 | $6,650.00 |
| 1,000 | $11.85 | $11,850.00 |
ADC12DL040CIVS 개요
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that processes input samples through a cascade of low-resolution flash stages with inter-stage digital error correction. Pipelined ADCs occupy the middle ground between flash converters (highest speed, highest power) and successive-approximation register (SAR) ADCs (lower speed, lower power), making them the dominant architecture for communications baseband, IF sampling, CCD imaging, and multi-channel data acquisition where tens of MSPS at 8-14 bits are required. The ADC12DL040CIVS sits firmly in this niche as a dual-channel, 12-bit, 40 MSPS converter.
Key features include 69 dB typical SNR at fIN = 10 MHz, 85 dB typical SFDR at fIN = 10 MHz, ±0.3 LSB typical DNL, 2.4 V to 3.6 V digital output driver supply for flexible interfacing to lower-voltage FPGAs/ASICs, a duty cycle stabilizer for robust performance with non-50% clock duty cycles, a power-down mode, and a multiplexed output mode that places both channels on a single 12-bit bus. Industrial temperature range operation spans -40 °C to +85 °C.
The ADC12DL040 uses a switched-capacitor pipelined architecture with proprietary digital correction logic. Each channel contains an input sample-and-hold amplifier, a switched-capacitor multiplying-DAC front end, and successive flash stages producing 12-bit latency-corrected outputs. The internal precision reference is trimmed at the factory and is not user-adjustable, simplifying PCB layout while ensuring channel-to-channel gain matching within ±0.5 %.
Typical applications include IF/baseband sampling in communications receivers, dual-channel CCD imaging digitizers, medical ultrasound beamformers, portable test and measurement instruments, and multi-axis industrial data acquisition systems. The dual-channel integration halves board area versus two discrete single-channel ADCs and guarantees matched AC performance between channels.
When designing with this part, drive the analog inputs with a low-impedance op-amp buffer (such as the THS4631 or LMH6624) to avoid sample-and-hold distortion. The 50 Ω clock input is critical: drive it from a low-jitter source (sub-ps RMS) to maximize SNR at high input frequencies. Decouple AVDD and DVDD separately with 0.1 µF ceramic + 10 µF tantalum capacitors placed within 5 mm of each supply pin.
This page synthesizes distributor pricing, drop-in alternatives within the 64-pin TQFP footprint, and practical design notes not found in the manufacturer datasheet alone.
드롭인 대체품: ADC12DL040CIVS — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC12DL040CIVS (동일 폼 팩터 및 풋프린트) — 차이점: Number of Channels, Architecture, Resolution, Analog Supply Voltage, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC12DL040CIVS/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC12DL065CIVS/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC12040CIVY
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$5.52 / 개
데이터시트 보기 →ADC10D020CIVSX/NOPB
✅ 드롭인✓ 재고 있음
$10.85 / 개
데이터시트 보기 →ADC12DL040CIVS 최대 정격 & 전기적 특성
| 분해능 | 12 Bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate (per channel) | 40 MSPS |
| Architecture | Pipelined CMOS |
| Analog Supply Voltage | 3.0 V (2.7 V to 3.6 V range) |
| Digital Output Driver Supply | 2.4 V to 3.6 V (separate DVDD) |
| Power Dissipation (typical) | 210 mW |
| Power-Down Mode | Yes |
| SNR (fIN = 10 MHz) | 69 dB (typical) |
| SFDR (fIN = 10 MHz) | 85 dB (typical) |
| DNL (Differential Non-Linearity) | ±0.3 LSB (typical) |
| Internal Reference | Yes (factory-trimmed, not user-adjustable) |
| Sample-and-Hold | Internal, dual |
| Duty Cycle Stabilizer | Yes |
| Multiplexed Output Mode | Yes (channels share single 12-bit bus) |
| Output Format | Straight Binary, offset binary, 2's complement (per pin strapping) |
| Input Clock | Single-ended or differential; 50 Ω terminated internally |
| 동작 온도 | -40 °C to +85 °C (industrial) |
| 패키지 | 64-pin TQFP (PAG) 10x10 mm, surface-mount |
| Lead Finish / RoHS | Lead-free / RoHS status depends on orderable suffix (see datasheet ordering info) |
ADC12DL040CIVS 핀 구성
| 핀 1 | VINA — Analog input channel A positive |
| 핀 2 | VINA- — Analog input channel A negative (complementary) |
| 핀 3 | AGND — Analog ground |
| 핀 4 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 5 | VREF — Internal reference bypass / external reference input |
| 핀 6 | AGND — Analog ground |
| 핀 7 | VINB — Analog input channel B positive |
| 핀 8 | VINB- — Analog input channel B negative (complementary) |
| 핀 9 | AGND — Analog ground |
| 핀 10 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 11 | CLK_A — Channel A clock input (positive) |
| 핀 12 | CLK_A- — Channel A clock input (negative) |
| 핀 13 | AGND — Analog ground |
| 핀 14 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 15 | PD — Power-down control (active high) |
| 핀 16 | DCS — Duty cycle stabilizer enable |
| 핀 17 | MUX — Multiplexed output mode enable |
| 핀 18 | DGND — Digital ground |
| 핀 19 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| 핀 20 | D0_A — Channel A data bit 0 (LSB) |
| 핀 21 | D1_A — Channel A data bit 1 |
| 핀 22 | D2_A — Channel A data bit 2 |
| 핀 23 | D3_A — Channel A data bit 3 |
| 핀 24 | D4_A — Channel A data bit 4 |
| 핀 25 | D5_A — Channel A data bit 5 |
| 핀 26 | D6_A — Channel A data bit 6 |
| 핀 27 | D7_A — Channel A data bit 7 |
| 핀 28 | D8_A — Channel A data bit 8 |
| 핀 29 | D9_A — Channel A data bit 9 |
| 핀 30 | D10_A — Channel A data bit 10 |
| 핀 31 | D11_A — Channel A data bit 11 (MSB) |
| 핀 32 | DGND — Digital ground |
| 핀 33 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| 핀 34 | D0_B — Channel B data bit 0 (LSB) |
| 핀 35 | D1_B — Channel B data bit 1 |
| 핀 36 | D2_B — Channel B data bit 2 |
| 핀 37 | D3_B — Channel B data bit 3 |
| 핀 38 | D4_B — Channel B data bit 4 |
| 핀 39 | D5_B — Channel B data bit 5 |
| 핀 40 | D6_B — Channel B data bit 6 |
| 핀 41 | D7_B — Channel B data bit 7 |
| 핀 42 | D8_B — Channel B data bit 8 |
| 핀 43 | D9_B — Channel B data bit 9 |
| 핀 44 | D10_B — Channel B data bit 10 |
| 핀 45 | D11_B — Channel B data bit 11 (MSB) |
| 핀 46 | DGND — Digital ground |
| 핀 47 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| 핀 48 | OFR_A — Channel A out-of-range indicator |
| 핀 49 | OFR_B — Channel B out-of-range indicator |
| 핀 50 | DGND — Digital ground |
| 핀 51 | DRVDD — Digital output driver supply (2.4 V to 3.6 V) |
| 핀 52 | NC — Not connected (per datasheet) |
| 핀 53 | NC — Not connected (per datasheet) |
| 핀 54 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 55 | AGND — Analog ground |
| 핀 56 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 57 | NC — Not connected (per datasheet) |
| 핀 58 | NC — Not connected (per datasheet) |
| 핀 59 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 60 | AGND — Analog ground |
| 핀 61 | AVDD — Analog supply (+3.0 V nominal) |
| 핀 62 | NC — Not connected (per datasheet) |
| 핀 63 | NC — Not connected (per datasheet) |
| 핀 64 | AVDD — Analog supply (+3.0 V nominal) |
일반적인 애플리케이션
ADC12DL040CIVS 적합 용도: 6 애플리케이션s: Communications IF / Baseband Sampling, Medical Ultrasound Beamformer Front-End, Dual-Channel CCD / CMOS Image Digitizer, Portable Test & Measurement Instrumentation, Multi-Axis Industrial Data Acquisition, Radar / Lidar Baseband Digitization.
Communications IF / Baseband Sampling
The ADC12DL040CIVS suits IF and baseband sampling in software-defined radio receivers and broadband communications base stations. With 40 MSPS per channel and 69 dB SNR at fIN = 10 MHz, two independent channels can simultaneously digitize I/Q baseband or a single IF chain, halving board area versus two discrete single-channel ADCs. The 2.4-3.6 V separate digital output supply lets the ADC12DL040CIVS drive a 2.5 V FPGA logic bank without level shifters, simplifying PCB layout and reducing BOM cost in compact SDR modules.
추천
Medical Ultrasound Beamformer Front-End
The dual 12-bit 40 MSPS channels of the ADC12DL040CIVS are widely deployed in medical ultrasound beamformer front-ends. Each ADC12DL040CIVS handles two adjacent transducer elements simultaneously, with channel-to-channel gain matching enforced by the internal factory-trimmed reference. At 5-15 MHz ultrasound frequencies, 40 MSPS comfortably exceeds the Nyquist requirement, and 85 dB SFDR preserves harmonics-free echo signals. Multiple ADC12DL040CIVS parts are typically clocked from a single low-jitter PLL for phase-coherent array acquisition.
추천
Dual-Channel CCD / CMOS Image Digitizer
The ADC12DL040CIVS digitizes dual CCD or CMOS image sensor analog outputs in industrial and scientific cameras. The dual channel simultaneous sampling preserves pixel-by-pixel correlation between two sensor regions, while 12-bit resolution captures the dynamic range needed for color and low-light imaging. 210 mW typical power keeps thermal dissipation manageable in enclosed camera housings, and the integrated sample-and-hold eliminates the need for external track-and-hold amplifiers on each channel.
추천
Portable Test & Measurement Instrumentation
For handheld oscilloscopes, spectrum analyzers, and data loggers, the ADC12DL040CIVS delivers 12-bit resolution at 40 MSPS in a small 10x10 mm TQFP footprint. The single 3.0 V analog supply plus 2.4-3.6 V digital supply simplifies battery-powered designs, while 210 mW power dissipation keeps the device within portable instrument thermal budgets. The multiplexed output mode can route both channels through one 12-bit bus, reducing FPGA pin count in cost-sensitive instruments.
추천
Multi-Axis Industrial Data Acquisition
The ADC12DL040CIVS handles multi-axis vibration, strain gauge, and pressure transducer digitizers in industrial predictive-maintenance systems. Each part captures two sensor channels simultaneously, and stacking multiple ADC12DL040CIVS ICs in parallel expands channel count while sharing one low-jitter clock. The industrial -40 °C to +85 °C temperature range supports deployment in factory-floor enclosures, and the duty cycle stabilizer tolerates non-50% clock duty cycles common in industrial backplanes.
추천
Radar / Lidar Baseband Digitization
The ADC12DL040CIVS serves as the baseband digitizer in short-range automotive radar, security radar, and lidar receiver chains. With two simultaneous sampling channels and 69 dB SNR at 10 MHz, the device cleanly captures I/Q radar baseband returns from down-converted IF stages. The internal reference reduces external component count, which is critical for the small form factor of automotive-grade sensor modules. The TQFP-64 footprint also eases hand-rework during prototyping of radar front-ends.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC12DL040CIVS — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC12DL040CIVS/NOPB | ADC12DL065CIVS/NOPB | ADC12040CIVY | ADC10D020CIVSX/NOPB |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-pin TQFP (PAG) 10x10 mm | 64-pin TQFP (PAG) 10x10 mm - same | 64-pin TQFP (PAG) 10x10 mm - same | 64-pin TQFP (PAG) 10x10 mm - same | 64-pin TQFP (PAG) 10x10 mm - same |
| Resolution | 12 Bits | 12 Bits | 12 Bits | 12 Bits | 10 Bits |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 2 (dual) |
| Sample Rate (per channel) | 40 MSPS | 40 MSPS | 65 MSPS (+62.5%) | 40 MSPS | 20 MSPS (-50%) |
| Supply Voltage (Analog) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) | 3.0 V (2.7 V to 3.6 V) |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
주요 차별점
- Identical die with lead-free RoHS finish (vs ADC12DL040CIVS/NOPB)
- Higher sample rate in identical package (vs ADC12DL065CIVS/NOPB)
- Single-channel option for cost-down designs (vs ADC12040CIVY)
설계 노트
Estimated: separate the analog (AVDD) and digital (DRVDD) power planes, and join them at a single point near the AGND/DGND pin junction. Place 0.1 µF ceramic + 10 µF tantalum decoupling pairs on every AVDD and DRVDD pin, within 5 mm of the IC. The analog inputs are sensitive to ground bounce, so route VIN± over a continuous ground plane and avoid crossing digital output traces on adjacent layers.
The CLK± pins require a low-jitter differential clock source; SNR degrades by 20·log10(1/(2π·fIN·t_jitter)) dB for a given input frequency. For 69 dB SNR at 10 MHz fIN, the clock RMS jitter must be below ~2 ps. Drive the CLK± pins through a 1:1 RF transformer (such as Mini-Circuits ADT1-1WT) from a clean oscillator or PLL output. Keep clock traces short, length-matched, and routed over a continuous ground plane.
Do not float the PD (power-down) pin — tie it low via a 10 kΩ resistor for normal operation. Leave the DCS (duty cycle stabilizer) pin enabled unless the source clock already has < 1 % duty-cycle error; disabling DCS with a non-50 % clock degrades SNR. For maximum SFDR, drive the analog inputs with a low-distortion, low-impedance op-amp such as the THS4631; passive RC networks alone are insufficient at IF frequencies.
Estimated: with 210 mW dissipation in a 64-pin TQFP (θJA ≈ 60 °C/W on a 4-layer JEDEC board), the junction temperature rise is approximately 12.6 °C above ambient, well within the 125 °C absolute maximum. If the ADC is deployed alongside other heat-dissipating components in a sealed enclosure, verify with thermal imaging under worst-case ambient. The exposed thermal pad is not present on this TQFP package, so all heat exits through the leads and PCB copper pour.
Route channel-A and channel-B analog input traces symmetrically, with matched length and identical via counts, to preserve channel-to-channel gain and phase matching. Place the input anti-aliasing RC network (typically 50 Ω + 10 pF) within 5 mm of each VIN± pin. Use a guard trace tied to analog ground around the input pair to reject digital noise coupling from the parallel data-bus traces below.
규정 준수 정보
RoHS/REACH/AEC-Q100 status not explicitly present in the verified web data; refer to the TI product page ordering table for the specific finish of the suffix shipped. Standard lead-free / NOPB variants are typically RoHS compliant; the bare CIVS suffix without /NOPB is generally the non-RoHS (lead-bearing) finish.
