ADS6144IRHB25 - 14-Bit 105MSPS Low-Power ADC | Texas Instruments
MPN: ADS6144IRHB25 ✓ Hoạt độngADS6144IRHB25 Tóm tắt
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time, continuous-amplitude analog input voltage into a discrete-time, discrete-amplitude digital code. Pipelined ADCs use a cascade of low-resolution flash stages with inter-stage digital error correction, achieving a practical trade-off between sampling rate (tens to hundreds of MSPS), resolution (10-16 bits), and power consumption. Within the broader signal chain hierarchy, an ADC sits between an analog front-end (amplifiers, filters, mixers) and a digital processor (DSP, FPGA, microcontroller), and is itself part of the larger class of data converters that also includes digital-to-analog converters (DACs).
Key features of the ADS6144IRHB25 include 105 MSPS maximum sample rate, 14-bit resolution, and a typical integral nonlinearity (INL) of +/-1.5 LSB at 105 MSPS. The device operates from a single 3.3 V analog supply and a 3.3 V (or selectable 1.8 V) digital supply, consuming approximately 130 mW at 105 MSPS in CMOS mode. Selectable parallel CMOS or LVDS outputs give designers the option to optimize for low-power I/O or high-noise-immunity backplane links, while internal references and an input common-mode buffer simplify the analog front-end design.
The ADS6144IRHB25 uses a multi-stage pipelined architecture with proprietary digital error correction, achieving an effective number of bits (ENOB) greater than 11 bits at the Nyquist frequency. An integrated high-bandwidth track-and-hold and on-chip reference deliver low aperture jitter and stable full-scale performance across temperature. The LVDS output mode doubles the maximum output data rate relative to CMOS, enabling efficient data transfer to FPGAs or DSPs without external bus drivers.
Typical applications include wireless communication base-station receivers, IF sampling in software-defined radio, portable ultrasound imaging front-ends, high-speed instrumentation, and CCD/CMOS imaging digitizers. The 105 MSPS rate is well-suited to IF-sampling architectures below 50 MHz input.
When designing with this device, ensure the analog input is driven by a low-impedance, AC- or DC-coupled amplifier with proper 50-ohm termination if the source is single-ended. Decouple both AVDD and DRVDD pins with low-ESR ceramic capacitors placed within 5 mm of the supply pins.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that augment the manufacturer datasheet for faster engineering selection.
Bộ thay thế dễ dàng lắp đặt cho ADS6144IRHB25 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADS6144IRHB25 (cùng hình factor và footprint) — khác nhau ở Input Type, Package, Output Interface, Resolution, Analog Supply Voltage.
ADS6142IRHB25
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS6143IRHB25
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS6145IRHB25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6144IRHBR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6144IRHBRG4
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS6144IRHB25 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 14 bits |
| Sample Rate | 105 MSPS (max) |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Type | Differential analog |
| Analog Supply Voltage | 3.3 V (typical) |
| Digital Supply Voltage | 3.3 V or 1.8 V (selectable) |
| Output Interface | Selectable parallel CMOS or LVDS |
| Integral Nonlinearity (INL) | +/-1.5 LSB (typ at 105 MSPS) |
| Differential Nonlinearity (DNL) | +/-0.5 LSB (typ) |
| Effective Number of Bits (ENOB) | 11 bits (typ at Nyquist) |
| Power Consumption | 130 mW (typ at 105 MSPS, CMOS mode) |
| Khoảng nhiệt độ hoạt động | -40C to +85C (industrial) |
| Hộp | 32-pin VQFN (5x5 mm, RHB) |
| Kiểu lắp đặt | Surface Mount |
| Cấp MSL | 2 (per JEDEC J-STD-020) |
| Trạng thái RoHS | Compliant |
| Lead Finish | NiPdAu (lead-free) |
Cấu hình chân ADS6144IRHB25
| Chân 1 | AVDD — Analog 3.3 V supply |
| Chân 2 | INP — Differential analog input positive |
| Chân 3 | INN — Differential analog input negative |
| Chân 4 | VCM — Common-mode voltage output |
| Chân 5 | AGND — Analog ground |
| Chân 6 | REFT — Internal reference top (decouple) |
| Chân 7 | REFB — Internal reference bottom (decouple) |
| Chân 8 | AGND — Analog ground |
| Chân 9 | DRVDD — Digital output supply (3.3 V or 1.8 V) |
| Chân 10 | DRGND — Digital ground |
| Chân 11 | D0 — Data output bit 0 (LSB) |
| Chân 12 | D1 — Data output bit 1 |
| Chân 13 | D2 — Data output bit 2 |
| Chân 14 | D3 — Data output bit 3 |
| Chân 15 | D4 — Data output bit 4 |
| Chân 16 | D5 — Data output bit 5 |
| Chân 17 | D6 — Data output bit 6 |
| Chân 18 | D7 — Data output bit 7 |
| Chân 19 | D8 — Data output bit 8 |
| Chân 20 | D9 — Data output bit 9 |
| Chân 21 | D10 — Data output bit 10 |
| Chân 22 | D11 — Data output bit 11 |
| Chân 23 | D12 — Data output bit 12 |
| Chân 24 | D13 — Data output bit 13 (MSB) |
| Chân 25 | DRGND — Digital ground |
| Chân 26 | CLKOUT — Clock output (DDR in LVDS mode) |
| Chân 27 | CLKP — Differential clock input positive |
| Chân 28 | CLKN — Differential clock input negative |
| Chân 29 | LVDS/CMOS — Output interface select |
| Chân 30 | PDN — Power-down (active low) |
| Chân 31 | RESET — Reset (active low) |
| Chân 32 | DRVDD — Digital output supply (3.3 V or 1.8 V) |
Ứng dụng tiêu biểu
ADS6144IRHB25 phù hợp cho 6 Áp dụngs: Wireless Base-Station Receiver, Software-Defined Radio IF Sampling, Portable Ultrasound Imaging, High-Speed Test and Measurement, CCD/CMOS Image Sensor Digitization, Industrial Process Control Instrumentation.
Wireless Base-Station Receiver
The ADS6144IRHB25 is well-suited for IF-sampling stages in wireless base-station receivers because its 105 MSPS sample rate comfortably digitizes IF bands up to 50 MHz while 11-bit ENOB at Nyquist preserves demodulation SNR. The selectable LVDS output mode lets it drive an FPGA or DSP across a backplane with high noise immunity, reducing the need for external bus drivers. Designers benefit from the integrated input common-mode buffer and internal reference that simplify the analog front-end, while the 3.3 V analog supply aligns with typical RF transceiver rails. Power consumption near 130 mW supports thermally-constrained multi-channel receiver cards.
Được đề xuất
Software-Defined Radio IF Sampling
In software-defined radio (SDR) platforms the ADS6144IRHB25 provides a low-power ADC front-end that digitizes the IF stage so that channelization, demodulation, and filtering are all done in software. Its 105 MSPS rate and 14-bit resolution cover HF/VHF/UHF IFs typical in SDR architectures below 50 MHz, while selectable CMOS or LVDS outputs let the same board interface to either an FPGA or a low-cost DSP. The pipelined architecture delivers consistent ENOB above 11 bits at Nyquist, which translates to usable dynamic range for narrowband signals and the ability to oversample wider bands. Industrial temperature grade makes the part suitable for outdoor or vehicular SDR nodes.
Được đề xuất
Portable Ultrasound Imaging
Ultrasound imaging front-ends require ADCs with sufficient sample rate to capture the band-limited transducer echo and adequate dynamic range to preserve low-contrast tissue information. The ADS6144IRHB25's 105 MSPS rate and 11-bit ENOB at Nyquist are well-matched to mid-range ultrasound channels with center frequencies of 5-20 MHz sampled at IF or directly. The selectable LVDS outputs enable high-speed transfer to an FPGA-based beamformer with minimal EMI, and the low 130 mW power consumption supports battery-driven portable carts. The 32-pin VQFN footprint fits compact channel-board layouts typical of phased-array probes.
Được đề xuất
High-Speed Test and Measurement
Bench-top instruments such as oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers leverage the ADS6144IRHB25's 105 MSPS sample rate and 14-bit resolution for digitizing analog test signals. The pipelined architecture provides low aperture jitter for accurate time-domain captures, while selectable LVDS outputs reduce digital switching noise coupling back into the analog front-end. The integrated reference and on-chip input buffer simplify calibration and reduce the bill of materials, which lowers total instrument cost. Industrial temperature rating allows the part to be used in production-floor test equipment that operates in non-controlled environments.
Được đề xuất
CCD/CMOS Image Sensor Digitization
Industrial camera systems that digitize analog CCD or CMOS sensor outputs benefit from the ADS6144IRHB25's combination of 105 MSPS rate and selectable CMOS or LVDS output flexibility. The pipelined architecture delivers consistent linearity required for high-fidelity image capture, while 14-bit resolution preserves dynamic range for high-contrast scenes. The 32-pin VQFN package fits compact camera head electronics, and the 3.3 V analog supply is compatible with most sensor bias rails. Designers can pair the ADC with an FPGA to perform real-time color interpolation, white balance, and compression in the digital domain.
Được đề xuất
Industrial Process Control Instrumentation
Process-control modules that monitor vibration, strain, or acoustic emission signals use the ADS6144IRHB25 to digitize high-bandwidth transducer outputs. The 105 MSPS rate oversamples these signals well above their Nyquist frequency, enabling digital filtering and decimation in an FPGA or DSP downstream. Industrial -40C to +85C temperature range ensures operation in factory-floor enclosures, and the selectable LVDS mode supports long board-to-board traces inside machinery. The pipelined architecture provides low INL and DNL for accurate amplitude measurement required for predictive maintenance and condition monitoring.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADS6144IRHB25 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADS6142IRHB25 | ADS6143IRHB25 | ADS6145IRHB25 | ADS6144IRHBR | ADS6144IRHBRG4 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-32 (RHB, 5x5 mm) | VQFN-32 (RHB, 5x5 mm) - same | VQFN-32 (RHB, 5x5 mm) - same | VQFN-32 (RHB, 5x5 mm) - same | VQFN-32 (RHB, 5x5 mm) - same | VQFN-32 (RHB, 5x5 mm) - same |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits |
| Sample Rate (max) | 105 MSPS | 65 MSPS (-38%) | 80 MSPS (-24%) | 125 MSPS (+19%) | 105 MSPS | 105 MSPS |
| Output Interface | Selectable CMOS or LVDS | Selectable CMOS or LVDS | Selectable CMOS or LVDS | Selectable CMOS or LVDS | Selectable CMOS or LVDS | Selectable CMOS or LVDS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS / Lead-Free | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
Bảo phân biệt quan trọng
- Selectable CMOS or LVDS output interface (vsADS6144IRHBR (same die, different reel))
- Speed grade exactly matched to mid-bandwidth designs (vsADS6145IRHB25)
- Upward compatible to faster family members (vsADS6142IRHB25)
Ghi chú thiết kế
Estimated: The 32-pin VQFN (RHB) package has an exposed thermal pad on pin 33 (EP). This pad MUST be soldered to a grounded copper pour that extends at least 8 vias to the inner ground plane to meet datasheet thermal resistance of approximately 30 C/W. Place 0.1 uF and 10 uF low-ESR ceramic decoupling capacitors within 5 mm of each AVDD and DRVDD pin to suppress switching noise coupling into the analog front-end.
The analog inputs (INP, INN) are differential and should be driven by a low-noise, low-distortion amplifier with proper 100-ohm differential termination across the input pins. Use a transformer or differential driver such as the OPA1612 for AC-coupled applications, or a fully differential amplifier for DC-coupled designs. Route the input traces as a 100-ohm differential pair with matched length and keep them away from the digital output bus and clock traces to avoid coupling.
Estimated: Do not exceed the maximum AVDD of 3.6 V or apply analog input levels above the common-mode range of 1.5 V to avoid damage. When switching from CMOS to LVDS mode, change DRVDD first and confirm the LVDS/CMOS pin state before reset release; otherwise the outputs may draw excess current. The internal reference pins REFT and REFB each require a 0.1 uF ceramic decoupling capacitor to AGND placed within 3 mm - omitting these capacitors will degrade SNR.
Thông tin tuân thủ
RoHS and REACH compliant per TI product page. Industrial temperature grade (-40C to +85C) only; AEC-Q100 automotive qualification NOT available - select ADS6144-Q1 for automotive.
