ADS6224IRGZ25 - Dual 12-Bit 105MSPS ADC LVDS | Texas Instruments
MPN: ADS6224IRGZ25 ✓ Hoạt độngADS6224IRGZ25 Tóm tắt
A pipelined ADC is a high-speed data-converter architecture that resolves each input sample through a chain of low-resolution stages with digital error correction, delivering high sample rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits). Pipelined ADCs sit higher than successive-approximation (SAR) ADCs in the speed/resolution trade-off but lower than flash ADCs in raw analog bandwidth; they are members of the broader data-converter IC family, which also includes delta-sigma, SAR, and flash topologies. The ADS6224 belongs to TI's high-speed converter portfolio targeting communications, instrumentation, and defense imaging subsystems.
Key features include a maximum sample rate of 125 MSPS (the 105-MSPS grade shipped as IRGZ25 is pin-compatible with the 65/80/105/125 MSPS variants), simultaneous sample-and-hold for both channels, a 3.5 dB coarse gain option plus a 6 dB programmable fine gain, serialized LVDS output for low-EMI high-speed data transfer, and a 1.8 V analog / 3.3 V LVDS supply split. Total power dissipation is approximately 320 mW per channel at 105 MSPS, and the LVDS interface reduces board-routing complexity versus parallel CMOS outputs at >100 MSPS.
The ADS6224 uses a multi-stage pipeline with an internal sample-and-hold and supports both single-wire and dual-wire LVDS serialization to flex with board density and FPGA capture budgets. Its LVDS topology generates far less switching noise than parallel CMOS outputs, easing EMI compliance in dense multi-channel systems such as 4G base-station receivers and phased-array radar digitizers.
Typical applications include communications base-station receivers (multi-carrier GSM, LTE, WCDMA), multi-channel wireless infrastructure, medical imaging front-ends (ultrasound beamformers), defense and instrumentation (synthetic aperture radar, oscilloscope data acquisition), and dual-channel IF-sampling designs where both I and Q paths must be digitized concurrently with matched gain.
When designing with this device, decouple AVDD (1.8 V) and LVDDR (3.3 V) supplies independently with 1 µF + 100 nF ceramic capacitors placed within 5 mm of the supply pins, and provide a solid low-impedance ground plane under the exposed thermal pad. Route the LVDS output pairs with 100 Ω differential impedance and length-match within 150 ps to minimize inter-symbol jitter at the FPGA receiver.
This page synthesizes distributor pricing, drop-in same-package alternatives (ADS6242IRGZR, ADS6243IRGZR, ADS6244IRGZRG4 from the same TI family), and practical design notes not found on the bare manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho ADS6224IRGZ25 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADS6224IRGZ25 (cùng hình factor và footprint) — khác nhau ở Operating Temperature Range, Package, Resolution, Input Type, Number of Channels.
ADS6242IRGZR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6243IRGZR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6244IRGZRG4
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS6245IRGZR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS6129IRGZ25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6224IRGZ25 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate (max) | 105 MSPS per channel |
| Sample Rate (family max) | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential, analog |
| Output Interface | Serialized LVDS (1-wire or 2-wire) |
| Analog Supply Voltage (AVDD) | 1.8 V |
| LVDS Supply Voltage (LVDDR) | 3.3 V |
| Reference | Internal (with external reference input option) |
| Programmable Gain | 3.5 dB coarse + 6 dB fine gain |
| Missing Codes | None (12-bit guaranteed) |
| Khoảng nhiệt độ hoạt động | -40 °C to +85 °C (industrial) |
| Hộp | 48-VQFN (RGZ) 7x7 mm with exposed thermal pad |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
Cấu hình chân ADS6224IRGZ25
| Chân 1 | AVDD — Analog 1.8 V supply |
| Chân 2 | AGND — Analog ground |
| Chân 3 | INP_A — Channel A positive analog input |
| Chân 4 | INN_A — Channel A negative analog input |
| Chân 5 | AGND — Analog ground |
| Chân 6 | VCM_A — Channel A common-mode voltage |
| Chân 7 | AVDD — Analog 1.8 V supply |
| Chân 8 | AGND — Analog ground |
| Chân 9 | INP_B — Channel B positive analog input |
| Chân 10 | INN_B — Channel B negative analog input |
| Chân 11 | AGND — Analog ground |
| Chân 12 | VCM_B — Channel B common-mode voltage |
| Chân 13 | REF — Reference voltage input/output |
| Chân 14 | REFT — Reference decoupling top |
| Chân 15 | REFB — Reference decoupling bottom |
| Chân 16 | REFM — Reference mid-rail |
| Chân 17 | AVDD — Analog 1.8 V supply |
| Chân 18 | AGND — Analog ground |
| Chân 19 | RESET — Hardware reset (active low) |
| Chân 20 | PDN — Power down (active high) |
| Chân 21 | SCLK — SPI clock |
| Chân 22 | SDATA — SPI data |
| Chân 23 | SDEN — SPI enable (active low) |
| Chân 24 | MODE — Output mode select (1-wire/2-wire LVDS) |
| Chân 25 | CLKP — Differential clock input positive |
| Chân 26 | CLKM — Differential clock input negative |
| Chân 27 | AVDD — Analog 1.8 V supply |
| Chân 28 | AGND — Analog ground |
| Chân 29 | NC — Not connected (per datasheet) |
| Chân 30 | NC — Not connected (per datasheet) |
| Chân 31 | DLVDS — LVDS supply 3.3 V |
| Chân 32 | DGND — Digital ground |
| Chân 33 | OUTAP — Channel A LVDS output positive |
| Chân 34 | OUTAN — Channel A LVDS output negative |
| Chân 35 | DLVDS — LVDS supply 3.3 V |
| Chân 36 | DGND — Digital ground |
| Chân 37 | OUTBP — Channel B LVDS output positive |
| Chân 38 | OUTBN — Channel B LVDS output negative |
| Chân 39 | DLVDS — LVDS supply 3.3 V |
| Chân 40 | DGND — Digital ground |
| Chân 41 | OUTCLK_P — LVDS clock output positive |
| Chân 42 | OUTCLK_N — LVDS clock output negative |
| Chân 43 | DLVDS — LVDS supply 3.3 V |
| Chân 44 | DGND — Digital ground |
| Chân 45 | DLVDS — LVDS supply 3.3 V |
| Chân 46 | DGND — Digital ground |
| Chân 47 | DLVDS — LVDS supply 3.3 V |
| Chân 48 | DGND — Digital ground |
Ứng dụng tiêu biểu
ADS6224IRGZ25 phù hợp cho 6 Áp dụngs: Communications Base-Station Receiver, Medical Ultrasound Beamformer, Defense & Instrumentation Data Acquisition, Wireless Multi-Channel Infrastructure, Dual-Channel IF Sampling Module, Industrial Process Control Signal Acquisition.
Communications Base-Station Receiver
The ADS6224IRGZ25 is well-suited for multi-carrier GSM/LTE/WCDMA base-station receiver IF sampling where two matched 12-bit channels digitize I and Q paths. Its 105 MSPS per channel comfortably handles 20 MHz LTE carriers with adequate margin for adjacent-channel rejection, while the serialized LVDS output reduces parallel-routing congestion on the board. The 1.8 V analog supply and dual-channel integration also help shrink the BOM versus two single-channel ADCs with separate references.
Được đề xuất
Medical Ultrasound Beamformer
In mid-tier ultrasound beamformer front-ends, the ADS6224IRGZ25 digitizes two channels at up to 105 MSPS, supporting 16-to-32-element phased-array probe multiplexing schemes. Its 12-bit resolution suits B-mode imaging at 40-60 dB dynamic range, and the LVDS interface keeps board density manageable inside compact handle assemblies. Dual simultaneous sampling ensures the matched time delay across I/Q acquisition paths required for accurate beam steering.
Được đề xuất
Defense & Instrumentation Data Acquisition
The ADS6224IRGZ25 serves in defense and test-and-measurement data-acquisition modules where dual matched channels digitize IF frequencies up to ~50 MHz with 12-bit amplitude resolution. The industrial -40 °C to +85 °C operating range ensures reliable operation in field-deployable chassis, and the serialized LVDS output minimizes radiated emissions — a key consideration for EMI-sensitive ISR and electronic-warfare subsystems.
Được đề xuất
Wireless Multi-Channel Infrastructure
In multi-antenna wireless infrastructure such as small-cell and picocell radios, the ADS6224IRGZ25 provides dual 12-bit channel digitization at 105 MSPS for diversity/MIMO digitizing stages. Its compact 48-VQFN footprint and low ~320 mW per channel dissipation reduce board thermal load, while serialized LVDS output routing keeps PCB trace counts tractable in tight 4-layer radio modules serving 4G/5G small cells.
Được đề xuất
Dual-Channel IF Sampling Module
The ADS6224IRGZ25 is purpose-built for dual-channel IF sampling where I and Q baseband or intermediate-frequency signals are digitized simultaneously with matched gain. Its simultaneous sample-and-hold eliminates timing skew between I/Q paths critical for vector signal analyzer accuracy, and the internal/external reference option lets designers tie the ADC to a shared system reference for absolute amplitude accuracy across multiple channels.
Được đề xuất
Industrial Process Control Signal Acquisition
In high-speed industrial process control modules such as vibration monitoring on rotating machinery, the ADS6224IRGZ25 digitizes two accelerometer/IEPE channels at 105 MSPS for spectrum analysis and bearing-fault detection. Its industrial temperature range and serialized LVDS interface suit deployment near motors and pumps, while the dual-channel integration halves board real-estate versus discrete single-channel solutions in DIN-rail or PLC form factors.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADS6224IRGZ25 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADS6242IRGZR | ADS6243IRGZR | ADS6244IRGZRG4 | ADS6245IRGZR | ADS6129IRGZ25 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm |
| Resolution | 12 bits | 12 bits | 14 bits | 14 bits | 14 bits | 12 bits |
| Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Sample Rate (max per channel) | 105 MSPS | 65 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 105 MSPS |
| Output Interface | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| LVDS Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Reference | Internal / External | Internal / External | Internal / External | Internal / External | Internal / External | Internal / External |
Bảo phân biệt quan trọng
- Same-package family continuity across 12-/14-bit and 65-125 MSPS (vsADS6244IRGZRG4)
- Serialized LVDS reduces pin count vs parallel-CMOS competitors (vsADS62P48IRGC25 (4-channel))
- Industrial -40 °C to +85 °C operating range (vsADS6129IRGZ25)
Ghi chú thiết kế
Decouple AVDD (1.8 V) and LVDDR (3.3 V) supplies independently with a 1 µF X7R ceramic in parallel with a 100 nF NP0/C0G ceramic placed within 5 mm of the respective supply pins. Route the analog and digital power planes as separate islands joined at a single point under the exposed thermal pad to prevent digital switching currents from coupling into the analog supply through the ground-return path.
Solder the exposed thermal pad (EP) directly to a continuous solid ground plane on the top PCB layer to provide a low-thermal-resistance path for internal dissipation (~320 mW per channel at 105 MSPS). Estimate: at +85 °C ambient and 700 mW total, junction temperature rise above ambient is approximately 30-40 °C with proper EP soldering — well within the 125 °C junction limit.
Route the LVDS output pairs (OUTAP/OUTAN, OUTBP/OUTBN, OUTCLK_P/OUTCLK_N) as 100 Ω differential microstrip with intra-pair length-matching within 150 ps (~25 mm at typical FR4 propagation) and keep the pair symmetric over a continuous reference plane. Keep LVDS traces away from the analog input pins (INP_A/INN_A, INP_B/INN_B) and the clock inputs (CLKP/CLKM) to avoid coupling noise back into the analog front-end.
Do not float the RESET or PDN pins — both must be driven actively (pull-up or driven high by the host) to ensure deterministic startup. The CLKP/CLKM differential clock must be low-jitter (<500 fs RMS) and AC-coupled with 0.1 µF caps for proper sampling; use a clock-cleaner/jitter-cleaner such as LMK04828 upstream of the ADC clock pin.
Thông tin tuân thủ
RoHS compliant per TI product page. AEC-Q100 not applicable for industrial-grade dual ADC; automotive users should consider the dedicated ADS62x4-Q1 variants.
