EP2C35F672C7N - 33K Logic Elements Cyclone II FPGA, 672-BGA | Altera / Intel
MPN: EP2C35F672C7N ✓ Hoạt độngEP2C35F672C7N Tóm tắt
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory blocks, and programmable interconnect, all of which can be reconfigured by the designer after manufacture. FPGAs occupy the top of the programmable logic hierarchy: programmable logic device (PLD) -> CPLD -> FPGA -> SoC FPGA. Compared with CPLDs, FPGAs offer far higher logic capacity, embedded Block RAM, DSP blocks, and high-speed transceiver capability, but require external configuration memory and a more complex power-up sequence.
Key features include 33,216 logic elements (LEs) arranged in 2,100 logic array blocks (LABs), 105 M9K embedded memory blocks delivering 483,840 bits total RAM, 35 embedded 18 x 18 multipliers for DSP operations, and four phase-locked loops (PLLs) for clock management. The device supports DDR/DDR2/QDRII SDRAM interfaces through dedicated external memory interfaces and offers 475 user I/O pins arranged in 8 I/O banks supporting LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards.
Cyclone II devices are SRAM-based, so the configuration bitstream must be loaded from an external flash or a configuration controller on every power-up. The EP2C35F672C7N supports Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), and JTAG configuration modes. Quartus II design software (legacy; current support is via Intel Quartus Prime with Cyclone II device support) is used for synthesis, place-and-route, and timing closure.
Typical applications include industrial motor control, video surveillance and image processing, low-cost protocol bridging (PCI to local bus, Ethernet MAC), consumer audio/video processing, and telecom line-card glue logic. The 672-BGA FineLine package provides a 27 x 27 mm footprint with 1.0 mm ball pitch, suitable for multi-layer PCBs using standard BGA assembly processes.
When designing with this part, plan a multi-rail power tree (1.2 V core, 2.5 V/3.3 V analog PLLs, I/O bank voltages), respect simultaneous switching output (SSO) limits per bank, and provide decoupling per Cyclone II handbook guidelines. The Cyclone II family is in mature production but has been surpassed by Cyclone IV/V/10 LP for new designs; sourcing risk should be evaluated for long-life programs.
This page synthesizes distributor pricing, drop-in pin-compatible Cyclone II alternatives, and practical design notes not found in the manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho EP2C35F672C7N — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP2C35F672C7N (cùng hình factor và footprint) — khác nhau ở Package, Speed Grade, Operating Temperature, Process Technology, RoHS Status.
EP2C35F672C6N
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP2C35F672C8N
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP2C35F672I8N
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP2C35F672C7
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP2C50F672C7N
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP2C35F672C7N Tỷ lệ tối đa & tính chất điện
| Family | Cyclone II |
| Logic Elements (LEs) | 33,216 |
| Logic Array Blocks (LABs) | 2,100 |
| Total Memory Bits | 483,840 bits |
| Embedded Multipliers (18x18) | 35 |
| Phase-Locked Loops (PLLs) | 4 |
| User I/O Pins | 475 |
| I/O Banks | 8 |
| Process Technology | 90 nm CMOS |
| Core Supply Voltage | 1.2 V |
| Nhiệt độ hoạt động | 0 °C to +85 °C (commercial) |
| Speed Grade | -7 |
| Hộp | 672-ball FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch |
| Kiểu lắp đặt | Surface Mount |
Cấu hình chân EP2C35F672C7N
| Chân 1 | I/O Bank 1A — User I/O / power per BGA ball map (see device pin tables) |
| Chân 2 | I/O Bank 1A — User I/O / power per BGA ball map |
| Chân 3 | VCCIO1 — I/O bank 1 reference voltage |
| Chân 4 | I/O Bank 1A — User I/O |
| Chân 5 | GND — Ground |
| Chân 6 | I/O Bank 1A — User I/O |
| Chân 7 | I/O Bank 1A — User I/O |
| Chân 8 | VCCINT — Core 1.2 V supply |
| Chân 9 | I/O Bank 1B — User I/O |
| Chân 10 | I/O Bank 1B — User I/O |
| Chân 11 | GND — Ground |
| Chân 12 | I/O Bank 1B — User I/O |
| Chân 13 | VCCIO1 — I/O bank 1 reference voltage |
| Chân 14 | I/O Bank 2A — User I/O |
| Chân 15 | I/O Bank 2A — User I/O |
| Chân 16 | GND — Ground |
| Chân 17 | I/O Bank 2A — User I/O |
| Chân 18 | I/O Bank 2A — User I/O |
| Chân 19 | VCCINT — Core 1.2 V supply |
| Chân 20 | I/O Bank 2B — User I/O |
| Chân 21 | I/O Bank 2B — User I/O |
| Chân 22 | GND — Ground |
| Chân 23 | I/O Bank 2B — User I/O |
| Chân 24 | VCCIO2 — I/O bank 2 reference voltage |
| Chân 25 | I/O Bank 3A — User I/O |
| Chân 26 | I/O Bank 3A — User I/O |
| Chân 27 | GND — Ground |
| Chân 28 | I/O Bank 3A — User I/O |
| Chân 29 | I/O Bank 3A — User I/O |
| Chân 30 | VCCINT — Core 1.2 V supply |
| Chân 31 | I/O Bank 3B — User I/O |
| Chân 32 | I/O Bank 3B — User I/O |
| Chân 33 | GND — Ground |
| Chân 34 | I/O Bank 3B — User I/O |
| Chân 35 | VCCIO3 — I/O bank 3 reference voltage |
| Chân 36 | I/O Bank 4A — User I/O |
| Chân 37 | I/O Bank 4A — User I/O |
| Chân 38 | GND — Ground |
| Chân 39 | I/O Bank 4A — User I/O |
| Chân 40 | I/O Bank 4A — User I/O |
| Chân 41 | VCCINT — Core 1.2 V supply |
| Chân 42 | I/O Bank 4B — User I/O |
| Chân 43 | I/O Bank 4B — User I/O |
| Chân 44 | GND — Ground |
| Chân 45 | I/O Bank 4B — User I/O |
| Chân 46 | VCCIO4 — I/O bank 4 reference voltage |
| Chân 47 | I/O Bank 5A — User I/O |
| Chân 48 | I/O Bank 5A — User I/O |
| Chân 49 | GND — Ground |
| Chân 50 | I/O Bank 5A — User I/O |
| Chân 51 | I/O Bank 5A — User I/O |
| Chân 52 | VCCINT — Core 1.2 V supply |
| Chân 53 | I/O Bank 5B — User I/O |
| Chân 54 | I/O Bank 5B — User I/O |
| Chân 55 | GND — Ground |
| Chân 56 | I/O Bank 5B — User I/O |
| Chân 57 | VCCIO5 — I/O bank 5 reference voltage |
| Chân 58 | I/O Bank 6A — User I/O |
| Chân 59 | I/O Bank 6A — User I/O |
| Chân 60 | GND — Ground |
| Chân 61 | I/O Bank 6A — User I/O |
| Chân 62 | I/O Bank 6A — User I/O |
| Chân 63 | VCCINT — Core 1.2 V supply |
| Chân 64 | I/O Bank 6B — User I/O |
| Chân 65 | I/O Bank 6B — User I/O |
| Chân 66 | GND — Ground |
| Chân 67 | I/O Bank 6B — User I/O |
| Chân 68 | VCCIO6 — I/O bank 6 reference voltage |
| Chân 69 | I/O Bank 7A — User I/O |
| Chân 70 | I/O Bank 7A — User I/O |
| Chân 71 | GND — Ground |
| Chân 72 | I/O Bank 7A — User I/O |
| Chân 73 | I/O Bank 7A — User I/O |
| Chân 74 | VCCINT — Core 1.2 V supply |
| Chân 75 | I/O Bank 7B — User I/O |
| Chân 76 | I/O Bank 7B — User I/O |
| Chân 77 | GND — Ground |
| Chân 78 | I/O Bank 7B — User I/O |
| Chân 79 | VCCIO7 — I/O bank 7 reference voltage |
| Chân 80 | I/O Bank 8A — User I/O |
| Chân 81 | I/O Bank 8A — User I/O |
| Chân 82 | GND — Ground |
| Chân 83 | I/O Bank 8A — User I/O |
| Chân 84 | I/O Bank 8A — User I/O |
| Chân 85 | VCCINT — Core 1.2 V supply |
| Chân 86 | I/O Bank 8B — User I/O |
| Chân 87 | I/O Bank 8B — User I/O |
| Chân 88 | GND — Ground |
| Chân 89 | I/O Bank 8B — User I/O |
| Chân 90 | VCCIO8 — I/O bank 8 reference voltage |
| Chân 91 | TMS — JTAG test mode select |
| Chân 92 | TCK — JTAG test clock |
| Chân 93 | TDO — JTAG test data out |
| Chân 94 | TDI — JTAG test data in |
| Chân 95 | nSTATUS — Configuration status (active-low) |
| Chân 96 | nCONFIG — Configuration start (active-low) |
| Chân 97 | DCLK — Configuration clock input |
| Chân 98 | DATA0 — Configuration data input |
| Chân 99 | MSEL0 — Configuration mode select 0 |
| Chân 100 | MSEL1 — Configuration mode select 1 |
Ứng dụng tiêu biểu
EP2C35F672C7N phù hợp cho 6 Áp dụngs: Industrial Motor Control, Video Surveillance and Image Processing, Low-Cost Protocol Bridging, Telecom Line-Card Glue Logic, Consumer Audio / Video Processing, Test and Measurement Instrumentation.
Industrial Motor Control
The EP2C35F672C7N is well suited to industrial motor-control designs where a deterministic FPGA must close current and torque loops in real time. With 35 dedicated 18 x 18 multipliers, the device can run field-oriented control (FOC) algorithms, space-vector PWM, and encoder decoding in a single chip, eliminating the need for a separate DSP. The 475 user I/Os are sufficient to drive multi-axis power stages, gate drivers, and resolver/encoder interfaces simultaneously, while the 1.2 V core and 90 nm CMOS process keep dynamic power within industrial thermal budgets. Designers typically pair the FPGA with external op-amps and isolated gate drivers, using the 4 PLLs to derive switching frequencies from a single crystal.
Được đề xuất
Video Surveillance and Image Processing
For multi-channel video surveillance and image processing, the EP2C35F672C7N offers 483,840 bits of Block RAM that can buffer full HD lines while the embedded multipliers execute 2-D FIR filters, motion estimation, or H.264 preprocessing. Its 475 user I/Os can ingest parallel ITU-R BT.656 / BT.1120 streams from multiple camera sensors and drive a parallel display bus or a DDR2 SDRAM controller. The 4 PLLs provide the flexible clock tree required for pixel-clock, memory-clock, and video-output domains, and the 672-FBGA exposes enough pins to keep DDR2 byte lanes isolated for signal integrity on a multi-layer PCB.
Được đề xuất
Low-Cost Protocol Bridging
The EP2C35F672C7N excels at protocol bridging, where one bus standard must be translated to another in legacy or mixed-voltage systems. The device's 475 user I/Os support multi-bank I/O standards, so designers can run 3.3 V LVTTL legacy logic on one bank and 2.5 V SSTL memory on another while bridging PCI / PCIe-like local bus, UART, SPI, I2C, and Ethernet MAC interfaces in fabric. With 33,216 LEs, multiple protocol cores can be instantiated concurrently without timing closure issues, and the 672-FBGA's high ball count makes it practical to keep each bus on dedicated banks to simplify PCB routing.
Được đề xuất
Telecom Line-Card Glue Logic
In telecom line cards the EP2C35F672C7N is frequently used as glue logic between network processors, TDM framers, and backplane SERDES, replacing multiple discrete CPLDs and bus transceivers. Its 33,216 LEs accommodate TDM crossbars, UTOPIA / POS-PHY interfaces, and custom HDLC framers, while 35 multipliers can run voice codecs or echo-cancellation DSP at low channel counts. The 475 user I/Os provide ample LVDS pairs for backplane interconnect, and the 1.2 V core / 90 nm process deliver low static power suitable for always-on line-card applications.
Được đề xuất
Consumer Audio / Video Processing
Consumer audio and video products benefit from the EP2C35F672C7N's combination of DSP-capable multipliers and high Block RAM in a low-cost FBGA. The device can implement custom audio sample-rate converters, multi-channel SPDIF/HDMI audio embedders, and display-scalers, while its 475 user I/Os handle parallel RGB / LVDS panel interfaces and I2S / TDM audio buses. Designers targeting mid-volume consumer SKUs can replace an ASIC with this Cyclone II part, gaining late-stage firmware updates without retooling the silicon.
Được đề xuất
Test and Measurement Instrumentation
In test and measurement instruments the EP2C35F672C7N provides the deterministic fabric required for custom timing engines, pattern generators, and high-speed digitizer front-ends. Its 475 user I/Os allow direct capture from parallel ADCs and DACs up to LVDS rates, while 35 multipliers and 483,840 bits of Block RAM can implement real-time DSP for FFTs, FIR filters, and statistical analyzers. The 672-FBGA exposes enough pins to maintain separate analog and digital grounds and to isolate trigger / clock domains, which is essential for low-noise measurement front ends.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP2C35F672C7N — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP2C35F672C6N | EP2C35F672C8N | EP2C35F672I8N | EP2C35F672C7 | EP2C50F672C7N |
|---|---|---|---|---|---|---|
| Package | 672-FBGA (27x27 mm) | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Logic Elements | 33,216 | 33,216 (same die) | 33,216 (same die) | 33,216 (same die) | 33,216 (same die) | 50,560 (larger die) |
| Block RAM (bits) | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 | 594,432 |
| 18x18 Multipliers | 35 | 35 | 35 | 35 | 35 | 86 |
| Speed Grade | -7 | -6 (slower Fmax) | -8 (faster Fmax) | -8 industrial temp | -7 same as target | -7 same as target |
| Operating Temperature | 0 C to +85 C (commercial) | 0 C to +85 C | 0 C to +85 C | -40 C to +100 C (industrial) | 0 C to +85 C | 0 C to +85 C |
| User I/O Pins | 475 | 475 | 475 | 475 | 475 | 450 |
Bảo phân biệt quan trọng
- Highest-density Cyclone II variant in the 672-FBGA footprint at -7 speed grade (vsEP2C20F672C7N)
- Same die across speed grades enables graceful Fmax tuning (vsEP2C35F672C6N)
- Industrial-temperature drop-in available without redesign (vsEP2C35F672I8N)
Ghi chú thiết kế
Cyclone II EP2C35 devices require a multi-rail power tree: 1.2 V VCCINT for the core, separate VCCIO supplies per I/O bank (1.5/1.8/2.5/3.3 V depending on the I/O standard), and 2.5 V analog supplies for each PLL (VCCA_PLL). Use a power-on reset supervisor with monotonic ramp times shorter than 100 ms and sequence VCCINT before VCCIO per the Cyclone II handbook. Decoupling: place 0.1 uF and 0.01 uF ceramics as close as practical to every VCCINT ball and one 10 uF bulk per VCCIO bank. Estimated: total decoupling capacitor count for a 672-FBGA EP2C35 board typically exceeds 60 ceramics.
The 672-FBGA uses a 1.0 mm ball pitch on a 27 x 27 mm body; follow Intel/Altera Cyclone II BGA PCB layout guidelines (via-in-pad recommended for breakout, microvia stackups allowed, 4 to 6 layer PCB minimum). Escape the outer two rows of balls with dog-bone fan-out and route differential pairs with matched lengths within 150 mil for LVDS. Provide at least one continuous ground plane adjacent to the BGA and stitch the perimeter with GND vias every 200 mil to control return paths.
Common Cyclone II design pitfalls: (1) forgetting to strap MSEL0/MSEL1 correctly for the desired configuration mode (AS/PS/FPP/JTAG); (2) leaving nCONFIG floating - it must be pulled high through 10 kohm; (3) using the wrong VCCIO voltage for SSTL or HSTL memories (2.5 V for DDR, 1.5 V for DDR2); (4) ignoring simultaneous-switching-output (SSO) limits per bank, which causes VCCIO droop and signal-integrity failures. Always run Quartus II / Quartus Prime PowerPlay power analysis and TimeQuest timing closure before tape-out.
Cyclone II EP2C35F672 devices use junction temperature ratings up to 100 C commercial and 125 C industrial. Estimated: typical utilization at 200 MHz with 60% logic toggling dissipates around 1.5 W to 2.5 W; with 8 layers of PCB copper and adequate airflow, theta_JA stays within Cyclone II handbook limits. For enclosed industrial enclosures without airflow, mount thermal vias under the BGA and use a 1 oz inner copper pour for VCCINT to spread heat.
Thông tin tuân thủ
Lead-free and Pb-free plating per Altera / Intel product marking. RoHS, REACH, and conflict-minerals declarations should be confirmed via the manufacturer product page or distributor CoC before high-volume release.
