Altera

EP2C35F672C7N - 33K Logic Elements Cyclone II FPGA, 672-BGA | Altera / Intel

料号： EP2C35F672C7N ✓ 量产中

有现货 1-3 个工作日内发货

1.2 V Vdss 672-ball FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch Package -7 Speed 483,840 bits Memory

低至 $98 USD / 件

最小起订量： 1 |

价格更新于： 2026-09-08

批量定价

数量	单价	小计
1	$150.46	$150.46
10	$142	$1,420.00
100	$128	$12,800.00
500	$112	$56,000.00
1,000	$98	$98,000.00

ℹ️ 所有价格均以 USD 计价

查看数据手册 (PDF) 查看替代料

数量

EP2C35F672C7N 概述

The Altera (now Intel) EP2C35F672C7N is a Cyclone II family Field-Programmable Gate Array (FPGA) delivering 33,216 logic elements, 483,840 total memory bits, and 475 user I/O pins in a 672-ball FineLine BGA package. Manufactured on a 1.2 V core, 90 nm CMOS process with a speed grade of -7 (commercial temperature range 0 °C to +85 °C), it targets cost-sensitive high-volume designs that previously required ASICs.

An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory blocks, and programmable interconnect, all of which can be reconfigured by the designer after manufacture. FPGAs occupy the top of the programmable logic hierarchy: programmable logic device (PLD) -> CPLD -> FPGA -> SoC FPGA. Compared with CPLDs, FPGAs offer far higher logic capacity, embedded Block RAM, DSP blocks, and high-speed transceiver capability, but require external configuration memory and a more complex power-up sequence.

Key features include 33,216 logic elements (LEs) arranged in 2,100 logic array blocks (LABs), 105 M9K embedded memory blocks delivering 483,840 bits total RAM, 35 embedded 18 x 18 multipliers for DSP operations, and four phase-locked loops (PLLs) for clock management. The device supports DDR/DDR2/QDRII SDRAM interfaces through dedicated external memory interfaces and offers 475 user I/O pins arranged in 8 I/O banks supporting LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards.

Cyclone II devices are SRAM-based, so the configuration bitstream must be loaded from an external flash or a configuration controller on every power-up. The EP2C35F672C7N supports Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), and JTAG configuration modes. Quartus II design software (legacy; current support is via Intel Quartus Prime with Cyclone II device support) is used for synthesis, place-and-route, and timing closure.

Typical applications include industrial motor control, video surveillance and image processing, low-cost protocol bridging (PCI to local bus, Ethernet MAC), consumer audio/video processing, and telecom line-card glue logic. The 672-BGA FineLine package provides a 27 x 27 mm footprint with 1.0 mm ball pitch, suitable for multi-layer PCBs using standard BGA assembly processes.

When designing with this part, plan a multi-rail power tree (1.2 V core, 2.5 V/3.3 V analog PLLs, I/O bank voltages), respect simultaneous switching output (SSO) limits per bank, and provide decoupling per Cyclone II handbook guidelines. The Cyclone II family is in mature production but has been surpassed by Cyclone IV/V/10 LP for new designs; sourcing risk should be evaluated for long-life programs.

This page synthesizes distributor pricing, drop-in pin-compatible Cyclone II alternatives, and practical design notes not found in the manufacturer datasheet.

直接替换替代料： EP2C35F672C7N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。

本系列中的变体

可与以下型号直接替换的同系列型号： EP2C35F672C7N （相同外形与封装尺寸） ——差异在于 Package, Speed Grade, Operating Temperature, Process Technology, RoHS Status.

EP2C35F672C6N

Intel

Operating Temperature: 0°C to 85°C (C6 speed grade, commercial)

RoHS Status: Lead-Free (per distributor listing)

对比 EP2C35F672C7N →

EP2C35F672C7

Intel

Package: 672-BGA (FineLine BGA)

Speed Grade: 7 (commercial)

Operating Temperature: 0C to +85C (commercial)

对比 EP2C35F672C7N →

EP2C35F672C8

Altera

Package: 672-BGA (FineLine BGA, 1.0 mm pitch)

Speed Grade: C8 (commercial, 8 ns pin-to-pin)

Process Technology: 90 nm

对比 EP2C35F672C7N →

EP2C35F672C8ES

Altera

Package: 672-ball FBGA (FineLine BGA), 26x26 mm

Operating Temperature: 0°C to +85°C (commercial)

RoHS Status: Compliant

对比 EP2C35F672C7N →

EP2C35F672C8N

Altera

Package: 672-BGA (FineLine BGA)

Speed Grade: C8

Operating Temperature: 0C to +85C (commercial)

对比 EP2C35F672C7N →

EP2C35F672I6N

Intel

Package: 672-ball FBGA (FineLine BGA), 27 mm

Speed Grade: 6

Operating Temperature: -40 C to +100 C (industrial, 'I' suffix)

对比 EP2C35F672C7N →

EP2C35F672I8

Intel

Package: 672-ball FineLine BGA (FBGA)

Speed Grade: 8 (C8 core)

Process Technology: 90 nm CMOS SRAM

对比 EP2C35F672C7N →

EP2C35F672I8N

Intel

Package: 672-BGA (FineLine)

Speed Grade: 8

Operating Temperature: -40C to +100C (industrial)

对比 EP2C35F672C7N →

✅ 直接替换 ⚠️ 规格未核验

Intel

📦 672-FBGA

Cyclone II · 50,528 · 594,432 · 594 Kbit (M4K blocks) · 450

✓ 有现货

$162.8 / 个

查看数据手册 →

EP2C35F672C7N 最大额定值与电气特性

Family	Cyclone II
Logic Elements (LEs)	33,216
Logic Array Blocks (LABs)	2,100
Total Memory Bits	483,840 bits
Embedded Multipliers (18x18)	35
Phase-Locked Loops (PLLs)	4
User I/O Pins	475
I/O Banks	8
Process Technology	90 nm CMOS
Core Supply Voltage	1.2 V
工作温度	0 °C to +85 °C (commercial)
Speed Grade	-7
封装	672-ball FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch
安装类型	Surface Mount

EP2C35F672C7N 引脚配置

引脚 1	I/O Bank 1A — User I/O / power per BGA ball map (see device pin tables)
引脚 2	I/O Bank 1A — User I/O / power per BGA ball map
引脚 3	VCCIO1 — I/O bank 1 reference voltage
引脚 4	I/O Bank 1A — User I/O
引脚 5	GND — Ground
引脚 6	I/O Bank 1A — User I/O
引脚 7	I/O Bank 1A — User I/O
引脚 8	VCCINT — Core 1.2 V supply
引脚 9	I/O Bank 1B — User I/O
引脚 10	I/O Bank 1B — User I/O
引脚 11	GND — Ground
引脚 12	I/O Bank 1B — User I/O
引脚 13	VCCIO1 — I/O bank 1 reference voltage
引脚 14	I/O Bank 2A — User I/O
引脚 15	I/O Bank 2A — User I/O
引脚 16	GND — Ground
引脚 17	I/O Bank 2A — User I/O
引脚 18	I/O Bank 2A — User I/O
引脚 19	VCCINT — Core 1.2 V supply
引脚 20	I/O Bank 2B — User I/O
引脚 21	I/O Bank 2B — User I/O
引脚 22	GND — Ground
引脚 23	I/O Bank 2B — User I/O
引脚 24	VCCIO2 — I/O bank 2 reference voltage
引脚 25	I/O Bank 3A — User I/O
引脚 26	I/O Bank 3A — User I/O
引脚 27	GND — Ground
引脚 28	I/O Bank 3A — User I/O
引脚 29	I/O Bank 3A — User I/O
引脚 30	VCCINT — Core 1.2 V supply
引脚 31	I/O Bank 3B — User I/O
引脚 32	I/O Bank 3B — User I/O
引脚 33	GND — Ground
引脚 34	I/O Bank 3B — User I/O
引脚 35	VCCIO3 — I/O bank 3 reference voltage
引脚 36	I/O Bank 4A — User I/O
引脚 37	I/O Bank 4A — User I/O
引脚 38	GND — Ground
引脚 39	I/O Bank 4A — User I/O
引脚 40	I/O Bank 4A — User I/O
引脚 41	VCCINT — Core 1.2 V supply
引脚 42	I/O Bank 4B — User I/O
引脚 43	I/O Bank 4B — User I/O
引脚 44	GND — Ground
引脚 45	I/O Bank 4B — User I/O
引脚 46	VCCIO4 — I/O bank 4 reference voltage
引脚 47	I/O Bank 5A — User I/O
引脚 48	I/O Bank 5A — User I/O
引脚 49	GND — Ground
引脚 50	I/O Bank 5A — User I/O
引脚 51	I/O Bank 5A — User I/O
引脚 52	VCCINT — Core 1.2 V supply
引脚 53	I/O Bank 5B — User I/O
引脚 54	I/O Bank 5B — User I/O
引脚 55	GND — Ground
引脚 56	I/O Bank 5B — User I/O
引脚 57	VCCIO5 — I/O bank 5 reference voltage
引脚 58	I/O Bank 6A — User I/O
引脚 59	I/O Bank 6A — User I/O
引脚 60	GND — Ground
引脚 61	I/O Bank 6A — User I/O
引脚 62	I/O Bank 6A — User I/O
引脚 63	VCCINT — Core 1.2 V supply
引脚 64	I/O Bank 6B — User I/O
引脚 65	I/O Bank 6B — User I/O
引脚 66	GND — Ground
引脚 67	I/O Bank 6B — User I/O
引脚 68	VCCIO6 — I/O bank 6 reference voltage
引脚 69	I/O Bank 7A — User I/O
引脚 70	I/O Bank 7A — User I/O
引脚 71	GND — Ground
引脚 72	I/O Bank 7A — User I/O
引脚 73	I/O Bank 7A — User I/O
引脚 74	VCCINT — Core 1.2 V supply
引脚 75	I/O Bank 7B — User I/O
引脚 76	I/O Bank 7B — User I/O
引脚 77	GND — Ground
引脚 78	I/O Bank 7B — User I/O
引脚 79	VCCIO7 — I/O bank 7 reference voltage
引脚 80	I/O Bank 8A — User I/O
引脚 81	I/O Bank 8A — User I/O
引脚 82	GND — Ground
引脚 83	I/O Bank 8A — User I/O
引脚 84	I/O Bank 8A — User I/O
引脚 85	VCCINT — Core 1.2 V supply
引脚 86	I/O Bank 8B — User I/O
引脚 87	I/O Bank 8B — User I/O
引脚 88	GND — Ground
引脚 89	I/O Bank 8B — User I/O
引脚 90	VCCIO8 — I/O bank 8 reference voltage
引脚 91	TMS — JTAG test mode select
引脚 92	TCK — JTAG test clock
引脚 93	TDO — JTAG test data out
引脚 94	TDI — JTAG test data in
引脚 95	nSTATUS — Configuration status (active-low)
引脚 96	nCONFIG — Configuration start (active-low)
引脚 97	DCLK — Configuration clock input
引脚 98	DATA0 — Configuration data input
引脚 99	MSEL0 — Configuration mode select 0
引脚 100	MSEL1 — Configuration mode select 1

典型应用

EP2C35F672C7N 适用于 6 应用s: Industrial Motor Control, Video Surveillance and Image Processing, Low-Cost Protocol Bridging, Telecom Line-Card Glue Logic, Consumer Audio / Video Processing, Test and Measurement Instrumentation.

🏭

Industrial Motor Control

The EP2C35F672C7N is well suited to industrial motor-control designs where a deterministic FPGA must close current and torque loops in real time. With 35 dedicated 18 x 18 multipliers, the device can run field-oriented control (FOC) algorithms, space-vector PWM, and encoder decoding in a single chip, eliminating the need for a separate DSP. The 475 user I/Os are sufficient to drive multi-axis power stages, gate drivers, and resolver/encoder interfaces simultaneously, while the 1.2 V core and 90 nm CMOS process keep dynamic power within industrial thermal budgets. Designers typically pair the FPGA with external op-amps and isolated gate drivers, using the 4 PLLs to derive switching frequencies from a single crystal.

推荐

🎥

Video Surveillance and Image Processing

For multi-channel video surveillance and image processing, the EP2C35F672C7N offers 483,840 bits of Block RAM that can buffer full HD lines while the embedded multipliers execute 2-D FIR filters, motion estimation, or H.264 preprocessing. Its 475 user I/Os can ingest parallel ITU-R BT.656 / BT.1120 streams from multiple camera sensors and drive a parallel display bus or a DDR2 SDRAM controller. The 4 PLLs provide the flexible clock tree required for pixel-clock, memory-clock, and video-output domains, and the 672-FBGA exposes enough pins to keep DDR2 byte lanes isolated for signal integrity on a multi-layer PCB.

推荐

MT47H64M16HR-25 (DDR2 SDRAM companion memory for frame buffer) EPCS64SI16N (Active-serial configuration memory for Cyclone II) EP2C35F672I8N · Intel

🌐

Low-Cost Protocol Bridging

The EP2C35F672C7N excels at protocol bridging, where one bus standard must be translated to another in legacy or mixed-voltage systems. The device's 475 user I/Os support multi-bank I/O standards, so designers can run 3.3 V LVTTL legacy logic on one bank and 2.5 V SSTL memory on another while bridging PCI / PCIe-like local bus, UART, SPI, I2C, and Ethernet MAC interfaces in fabric. With 33,216 LEs, multiple protocol cores can be instantiated concurrently without timing closure issues, and the 672-FBGA's high ball count makes it practical to keep each bus on dedicated banks to simplify PCB routing.

推荐

EP2C20F256C6N · Intel DP83848I (Ethernet PHY commonly bridged via MII/RMII to Cyclone II) EPCS16SI8N · Altera

🖥️

Telecom Line-Card Glue Logic

In telecom line cards the EP2C35F672C7N is frequently used as glue logic between network processors, TDM framers, and backplane SERDES, replacing multiple discrete CPLDs and bus transceivers. Its 33,216 LEs accommodate TDM crossbars, UTOPIA / POS-PHY interfaces, and custom HDLC framers, while 35 multipliers can run voice codecs or echo-cancellation DSP at low channel counts. The 475 user I/Os provide ample LVDS pairs for backplane interconnect, and the 1.2 V core / 90 nm process deliver low static power suitable for always-on line-card applications.

推荐

EP2C15AF256C8N · Intel EPCS64SI16N (Active-serial configuration memory) EP2C35F672C8N · Altera

🎧

Consumer Audio / Video Processing

Consumer audio and video products benefit from the EP2C35F672C7N's combination of DSP-capable multipliers and high Block RAM in a low-cost FBGA. The device can implement custom audio sample-rate converters, multi-channel SPDIF/HDMI audio embedders, and display-scalers, while its 475 user I/Os handle parallel RGB / LVDS panel interfaces and I2S / TDM audio buses. Designers targeting mid-volume consumer SKUs can replace an ASIC with this Cyclone II part, gaining late-stage firmware updates without retooling the silicon.

推荐

EP2C20F484C7N · Intel EPCS16SI8N · Altera EP2C35F484C7N · Intel

📺

Test and Measurement Instrumentation

In test and measurement instruments the EP2C35F672C7N provides the deterministic fabric required for custom timing engines, pattern generators, and high-speed digitizer front-ends. Its 475 user I/Os allow direct capture from parallel ADCs and DACs up to LVDS rates, while 35 multipliers and 483,840 bits of Block RAM can implement real-time DSP for FFTs, FIR filters, and statistical analyzers. The 672-FBGA exposes enough pins to maintain separate analog and digital grounds and to isolate trigger / clock domains, which is essential for low-noise measurement front ends.

推荐

EP2C50F672C8N · Intel EPCS64SI16N (Active-serial configuration memory for boot) EP2C35F672C6N · Intel

推荐产品汇总

EP2C20F484C6N Intel 用于： Industrial Motor Control EPCS16SI8N Altera 用于： Industrial Motor Control, Low-Cost Protocol Bridging, Consumer Audio / Video Processing EP2C35F672C6N Intel 用于： Industrial Motor Control, Test and Measurement Instrumentation MT47H64M16HR-25 DDR2 SDRAM companion memory for frame buffer 用于： Video Surveillance and Image Processing EPCS64SI16N Active-serial configuration memory for Cyclone II 用于： Video Surveillance and Image Processing, Telecom Line-Card Glue Logic, Test and Measurement Instrumentation EP2C35F672I8N Intel 用于： Video Surveillance and Image Processing EP2C20F256C6N Intel 用于： Low-Cost Protocol Bridging DP83848I Ethernet PHY commonly bridged via MII/RMII to Cyclone II 用于： Low-Cost Protocol Bridging EP2C15AF256C8N Intel 用于： Telecom Line-Card Glue Logic EP2C35F672C8N Altera 用于： Telecom Line-Card Glue Logic EP2C20F484C7N Intel 用于： Consumer Audio / Video Processing EP2C35F484C7N Intel 用于： Consumer Audio / Video Processing EP2C50F672C8N Intel 用于： Test and Measurement Instrumentation

What is the logic capacity of the EP2C35F672C7N?

The EP2C35F672C7N contains 33,216 logic elements organized into 2,100 logic array blocks (LABs), according to the Cyclone II device family datasheet (CII51001). It also provides 483,840 bits of embedded RAM in 105 M9K blocks and 35 dedicated 18 x 18 multipliers, making it one of the largest Cyclone II devices for cost-sensitive high-volume designs.

How many user I/O pins does the EP2C35F672C7N have?

The EP2C35F672C7N provides 475 user I/O pins distributed in 8 banks, according to the Cyclone II device handbook. The 672-ball FBGA package dedicates the remaining balls to power, ground, JTAG, configuration, and no-connect, supporting LVDS, LVCMOS, LVTTL, SSTL, and HSTL I/O standards across the banks.

Where can I buy the EP2C35F672C7N and what is the price?

The EP2C35F672C7N is available through authorized distributors including DigiKey and Mouser, as well as independent stockists such as Heisener and Win Source. As of 2026-09-08, Heisener quotes approximately $150.46 per unit with a reported stock of 33,960 pieces; distributor pricing varies by quantity break and current spot availability.

What is the lead time for the EP2C35F672C7N?

Heisener reports the EP2C35F672C7N can ship immediately, with estimated delivery of 2026-08-08 to 2026-08-13 for expedited orders, as of 2026-09-08. Lead time at franchise distributors such as DigiKey and Mouser typically ranges from same-day to several weeks depending on factory stock; request a quote to confirm current lead time before placing an order.

Is the EP2C35F672C7N in stock at distributors?

Yes, the EP2C35F672C7N is currently listed as in stock at Heisener (33,960 pieces reported as of 2026-09-08) and through DigiKey and Mouser channels. Because Cyclone II is a mature family, independent stockists frequently hold significant inventory; check distributor real-time stock and consider multiple sources for production-volume orders.

EP2C35F672C7N vs EP2C35F672I8N - which should I choose?

The EP2C35F672C7N is the commercial-temperature (-7 speed grade, 0 °C to +85 °C) variant, while the EP2C35F672I8N is the industrial-temperature (-8 speed grade, -40 °C to +100 °C) variant. Both share the same 672-FBGA package and pinout, so they are drop-in compatible at the PCB level. Choose the C7N for indoor/benign environments and the I8N when the design must survive extended industrial temperature ranges.

What is the difference between EP2C35F672C7N and EP2C35F484C6N?

The EP2C35F672C7N uses the 672-FBGA package with 475 user I/Os and is built around the -7 speed grade (faster), while the EP2C35F484C6N uses the smaller 484-FBGA package with 322 user I/Os and the slower -6 speed grade. Both deliver the same 33,216 logic elements internally. Choose EP2C35F672C7N when more I/O or higher Fmax is needed; choose EP2C35F484C6N when board space is at a premium.

When should I choose the EP2C35F672C7N over the EP2C20F484C7N?

Choose the EP2C35F672C7N when your design needs the higher logic capacity (33,216 vs 18,752 LEs), more user I/O (475 vs 315), more Block RAM (483,840 vs 239,616 bits), and the larger 672-FBGA package. Choose the EP2C20F484C7N when a smaller 484-FBGA footprint, lower cost, and reduced I/O count fit the application. Both share the same Cyclone II architecture, so Quartus II / Quartus Prime IP is portable.

What is the best drop-in replacement for the EP2C35F672C7N?

The best drop-in replacement is the EP2C35F672C7N with an alternative speed grade such as EP2C35F672C6N (slower -6 speed grade, same 672-FBGA, fully pin-to-pin) or EP2C35F672C8N (faster -8 speed grade in some distributions, same package). These variants share the same die and pinout; only the speed grade and operating temperature differ, making them mechanically and electrically drop-in.

Where can I download the EP2C35F672C7N datasheet PDF?

The official Cyclone II device family datasheet (document CII51001) is available from Intel (formerly Altera) at the Altera/Intel literature server, for example https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc2/cyc2_cii51001.pdf. Distributors such as DigiKey and Mouser also host a datasheet link on the EP2C35F672C7N product page for one-click PDF download.

Where can I find the pinout for the EP2C35F672C7N?

The pinout for the EP2C35F672C7N is documented in the Cyclone II device handbook pin tables (document CII51002 / CII5V1) and the device-specific addendum on the Intel literature server. The 672-ball FineLine BGA uses a 1.0 mm ball pitch on a 27 x 27 mm body; ball coordinates, bank assignments, and differential-pair maps are provided in the pin tables.

What is the difference between Cyclone II and Cyclone IV?

Cyclone II is built on a 90 nm process with 1.2 V core and uses older configuration schemes, while Cyclone IV is built on 60 nm with 1.0 V core (Cyclone IV E) or 1.1 V (Cyclone IV GX with transceivers). Cyclone IV adds 8B/10B capable transceivers on GX variants, more hardened memory blocks, and improved DSP blocks. The EP2C35F672C7N does not have a drop-in Cyclone IV equivalent because of package and voltage differences - migration requires board rework.

What are the key specifications of the EP2C35F672C7N that engineers should know?

Key specifications are: 33,216 logic elements, 483,840 bits of embedded Block RAM, 35 dedicated 18 x 18 multipliers, 4 PLLs, 475 user I/O pins in 8 banks, 1.2 V core on 90 nm CMOS, and a 672-ball FineLine BGA (27 x 27 mm, 1.0 mm pitch). Speed grade -7 (commercial, 0 °C to +85 °C) is the operating point. Configuration modes include AS, PS, FPP, and JTAG.

What is the best Xilinx or Lattice equivalent for the EP2C35F672C7N?

Cross-brand FPGAs in the same general capacity class include the Xilinx Spartan-3 XC3S1500 / XC3S2000 and the Lattice ECP2/ECP2M families; however, none of these are pin-to-pin drop-in replacements for the 672-FBGA EP2C35F672C7N because packages, ball maps, I/O standards, and voltage rails differ. Treat any Xilinx/Lattice part as a redesign alternative, not a drop-in substitute, and plan for PCB rework and firmware migration.

工程参考数据： EP2C35F672C7N ——对比、设计指导和合规信息。

选型指南

Choose the EP2C35F672C7N when the design needs Cyclone II's 33,216 LEs, 475 user I/Os, and 672-ball FBGA capacity at the -7 commercial speed grade, particularly for industrial motor control, video image processing, telecom line-card glue logic, and protocol-bridging designs where a 1.2 V core and 90 nm CMOS process deliver a favorable cost/performance trade-off. Choose the EP2C35F672C6N if timing closure is comfortable at a slower Fmax and lower cost is the priority. Choose the EP2C35F672I8N for industrial-temperature environments requiring operation down to -40 C. Choose the EP2C50F672C7N when you need even more logic (50,560 LEs) and RAM in the same 672-FBGA. Consider migrating to Cyclone IV E or Cyclone 10 LP for new designs where the Cyclone II supply chain or feature set is a concern.

与替代料对比

参数	本产品	EP2C35F672C6N	EP2C35F672C8N	EP2C35F672I8N	EP2C35F672C7	EP2C50F672C7N
Package	672-FBGA (27x27 mm)	672-FBGA (27x27 mm) - same	672-FBGA (27x27 mm) - same	672-FBGA (27x27 mm) - same	672-FBGA (27x27 mm) - same	672-FBGA (27x27 mm) - same
Brand	Altera / Intel	Altera / Intel	Altera / Intel	Altera / Intel	Altera / Intel	Altera / Intel
Logic Elements	33,216	33,216 (same die)	33,216 (same die)	33,216 (same die)	33,216 (same die)	50,560 (larger die)
Block RAM (bits)	483,840	483,840	483,840	483,840	483,840	594,432
18x18 Multipliers	35	35	35	35	35	86
Speed Grade	-7	-6 (slower Fmax)	-8 (faster Fmax)	-8 industrial temp	-7 same as target	-7 same as target
Operating Temperature	0 C to +85 C (commercial)	0 C to +85 C	0 C to +85 C	-40 C to +100 C (industrial)	0 C to +85 C	0 C to +85 C
User I/O Pins	475	475	475	475	475	450

关键差异点

Highest-density Cyclone II variant in the 672-FBGA footprint at -7 speed grade （对比 EP2C20F672C7N)
Same die across speed grades enables graceful Fmax tuning （对比 EP2C35F672C6N)
Industrial-temperature drop-in available without redesign （对比 EP2C35F672I8N)

设计说明

Cyclone II EP2C35 devices require a multi-rail power tree: 1.2 V VCCINT for the core, separate VCCIO supplies per I/O bank (1.5/1.8/2.5/3.3 V depending on the I/O standard), and 2.5 V analog supplies for each PLL (VCCA_PLL). Use a power-on reset supervisor with monotonic ramp times shorter than 100 ms and sequence VCCINT before VCCIO per the Cyclone II handbook. Decoupling: place 0.1 uF and 0.01 uF ceramics as close as practical to every VCCINT ball and one 10 uF bulk per VCCIO bank. Estimated: total decoupling capacitor count for a 672-FBGA EP2C35 board typically exceeds 60 ceramics.

The 672-FBGA uses a 1.0 mm ball pitch on a 27 x 27 mm body; follow Intel/Altera Cyclone II BGA PCB layout guidelines (via-in-pad recommended for breakout, microvia stackups allowed, 4 to 6 layer PCB minimum). Escape the outer two rows of balls with dog-bone fan-out and route differential pairs with matched lengths within 150 mil for LVDS. Provide at least one continuous ground plane adjacent to the BGA and stitch the perimeter with GND vias every 200 mil to control return paths.

Common Cyclone II design pitfalls: (1) forgetting to strap MSEL0/MSEL1 correctly for the desired configuration mode (AS/PS/FPP/JTAG); (2) leaving nCONFIG floating - it must be pulled high through 10 kohm; (3) using the wrong VCCIO voltage for SSTL or HSTL memories (2.5 V for DDR, 1.5 V for DDR2); (4) ignoring simultaneous-switching-output (SSO) limits per bank, which causes VCCIO droop and signal-integrity failures. Always run Quartus II / Quartus Prime PowerPlay power analysis and TimeQuest timing closure before tape-out.

Cyclone II EP2C35F672 devices use junction temperature ratings up to 100 C commercial and 125 C industrial. Estimated: typical utilization at 200 MHz with 60% logic toggling dissipates around 1.5 W to 2.5 W; with 8 layers of PCB copper and adequate airflow, theta_JA stays within Cyclone II handbook limits. For enclosed industrial enclosures without airflow, mount thermal vias under the BGA and use a 1 oz inner copper pour for VCCINT to spread heat.

合规信息

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

无铅

Yes

无卤

Unknown

冲突矿物

Unknown

Lead-free and Pb-free plating per Altera / Intel product marking. RoHS, REACH, and conflict-minerals declarations should be confirmed via the manufacturer product page or distributor CoC before high-volume release.

数据核验日期： 2026-09-08 ——数据由 XAIPART 元器件工程团队核验和整理

来源： Distributor, Distributor, Octopart, Distributor, Distributor, Distributor, Manufacturer Datasheet