EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel
MPN: EP910LI-35T ⚠ Lần mua cuốiEP910LI-35T Tóm tắt
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC historically used as a glue-logic replacement for multiple TTL/CMOS SSI/MSI parts. Sitting in the taxonomy between PAL/GAL and modern CPLD/FPGA, EPLDs offer deterministic combinational and registered logic with EPROM- or EEPROM-based configuration. The EP910 family from Intel/Altera represents one of the industry-standard Classic EPLD lines used in long-life-cycle industrial, military, and aerospace systems.
Key features include 24 macrocells with configurable I/O architecture, 450 usable gates, 35 ns tPD propagation delay, 28.6 MHz fMAX toggle frequency, and a single 5 V (4.75 V–5.25 V) supply. The device supports in-system programmability via Altera's classic programming algorithm and offers 10-year data retention thanks to EPROM-based configuration cells. The 44-pin PLCC package is JEDEC-standard and supports both socketed and surface-mount assembly.
The EP910LI-35T architecture combines a global interconnect matrix with per-macrocell product-term arrays, allowing wide AND-OR logic and buried register feedback. Compared with discrete TTL/MSI replacement, it reduces board area by typically 5:1 to 10:1 while improving timing predictability and reducing power consumption to CMOS levels at idle.
Typical applications include industrial control glue logic, military/aerospace retrofit boards, telecom interface adapters, and legacy peripheral controllers. The wide supply tolerance (4.75 V–5.25 V) makes it tolerant of legacy 5 V backplanes. The deterministic 35 ns delay simplifies worst-case timing closure in asynchronous control paths.
Designers should note that the EP910 family is in long-term support status - new designs are not recommended, but Obsolescence/EOL notifications typically allow multi-year last-time-buy windows via franchised distributors and aftermarket suppliers like Rochester Electronics. Programming requires Altera-supported hardware (e.g., Altera Logic Programmer or compatible).
This page synthesizes verified distributor pricing, drop-in replacement options (including the EP910LC and EP910ILC family variants), and practical design considerations not consolidated in the original datasheet.
Bộ thay thế dễ dàng lắp đặt cho EP910LI-35T — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP910LI-35T (cùng hình factor và footprint) — khác nhau ở Package, Technology, Mounting Type, Operating Temperature, Propagation Delay (tPD).
EP910LI-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910LC-35T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910LC-30T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910ILC-25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910ILC-15
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910LI-30T
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP910LI-35T Tỷ lệ tối đa & tính chất điện
| Family | Classic EPLD (EP910) |
| Logic Elements | 24 macrocells |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Toggle Frequency (fMAX) | 28.6 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, EPROM-based |
| Hộp | 44-pin PLCC (JEDEC) |
| Nhiệt độ hoạt động | -40C to +85C (industrial, 'I' suffix) |
| Kiểu lắp đặt | Surface Mount / Socket |
| Programming Method | EPROM (UV-erasable for windowed versions) |
Cấu hình chân EP910LI-35T
| Chân 1 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 2 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 3 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 4 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 5 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 6 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 7 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 8 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 9 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 10 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 11 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 12 | GND — Ground |
| Chân 13 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 14 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 15 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 16 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 17 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 18 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 19 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 20 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 21 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 22 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 23 | GND — Ground |
| Chân 24 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 25 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 26 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 27 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 28 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 29 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 30 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 31 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 32 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 33 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 34 | GND — Ground |
| Chân 35 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 36 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 37 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 38 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 39 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 40 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 41 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 42 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 43 | VCC — +5 V power supply |
| Chân 44 | VCC — +5 V power supply |
Ứng dụng tiêu biểu
EP910LI-35T phù hợp cho 6 Áp dụngs: Industrial Control Glue Logic, Military and Aerospace Retrofit Boards, Telecom Interface Adapters, Legacy Peripheral Controllers, Test and Measurement Instrumentation, Point-of-Sale and Retail Terminal Logic.
Industrial Control Glue Logic
The EP910LI-35T fits industrial control glue-logic applications because its 24 macrocells and 450 usable gates consolidate 5-10 standard 74-series TTL/MSI parts into a single non-volatile device, while the industrial temperature range (-40C to +85C) supports factory-floor PLC backplanes. The 35 ns tPD provides deterministic timing for asynchronous control paths in motor drives and conveyor controllers. The 5 V supply and TTL-compatible I/O allow direct drop-in replacement of legacy GAL/PAL devices on existing PCB footprints. Compared with discrete TTL logic, the EP910LI-35T reduces board area by approximately 5:1 to 10:1 while lowering idle power to CMOS levels.
Được đề xuất
Military and Aerospace Retrofit Boards
The EP910LI-35T is widely deployed in military and aerospace retrofit programs where its non-volatile EPROM configuration ensures instant-on behavior without external boot memory - critical for avionics and weapons-system interfaces. The industrial temperature range (-40C to +85C) and CMOS technology provide long-term reliability in vibration and thermal-cycling environments. The 35 ns tPD handles legacy MIL-STD-1553 and ARINC 429 interface timing without issues. Rochester Electronics' franchised long-term supply program supports multi-decade aerospace platform lifecycles. The 44-pin PLCC package accommodates conformal coating and ruggedization processes required by DO-160 and MIL-STD-810 environments.
Được đề xuất
Telecom Interface Adapters
The EP910LI-35T serves telecom interface adapters (T1/E1, RS-232/RS-485 glue logic, legacy PBX line cards) where its 24 macrocells handle protocol conversion and timing-recovery functions with deterministic 35 ns latency. The 5 V supply matches legacy telecom backplanes, and the 44-pin PLCC allows socketed field replacement - critical for service-depot maintenance. The non-volatile configuration eliminates in-system programming at power-up, supporting hot-swap and field-service workflows. The wide 4.75 V to 5.25 V supply tolerance handles voltage droop during line-card power events. Compared with modern CPLDs, the EP910LI-35T's 28.6 MHz fMAX is sufficient for sub-30 MHz telecom interface rates including ISDN BRI and H.110 bus compatibility.
Được đề xuất
Legacy Peripheral Controllers
The EP910LI-35T integrates ISA-bus peripheral controllers (parallel ports, SCSI adapters, floppy controllers) on legacy motherboards, where its 24 macrocells implement address decoding, wait-state generation, and interrupt prioritization. The 35 ns tPD supports ISA bus timing (8 MHz) without inserting wait states. The 5 V TTL-compatible I/O interfaces directly to ISA bus drivers without level translation. The 44-pin PLCC allows socketed upgrades for firmware revisions via EPROM erasure and reprogramming. Designers can consolidate 6-12 standard PAL/GAL devices into one EP910LI-35T, reducing motherboard BOM and improving reliability.
Được đề xuất
Test and Measurement Instrumentation
The EP910LI-35T fits test and measurement front-end logic (signal routing matrices, scan-chain controllers, custom waveform generators) because its deterministic 35 ns timing simplifies worst-case timing closure in instrumentation paths where PXI/VXI backplane timing is critical. The industrial temperature range supports lab-to-field deployment without redesign. The non-volatile EPROM configuration ensures repeatable test sequences without boot delays. The 24 macrocells handle 4-8 channels of multiplexed signal routing with per-channel enable logic. Compared with modern FPGAs, the EP910LI-35T offers instant-on deterministic behavior with no configuration bitstream validation overhead.
Được đề xuất
Point-of-Sale and Retail Terminal Logic
The EP910LI-35T serves point-of-sale terminals, barcode scanners, and receipt printers where its 24 macrocells consolidate I/O decoding, keypad scanning, and display-driving logic in a single 5 V device. The 35 ns tPD handles real-time keypad debounce and LCD multiplexing without timing issues. The non-volatile EPROM configuration supports firmware updates via windowed packages (ceramic versions) for service depot reprogramming. The industrial temperature range accommodates outdoor kiosk and refrigerated-cooler deployments. The 44-pin PLCC footprint supports socketed field replacement, minimizing service downtime. Compared with discrete CMOS logic, the EP910LI-35T reduces PCB area by 50-70% in cost-sensitive retail terminals.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP910LI-35T — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP910LI-35 | EP910LC-35T | EP910LC-30T | EP910ILC-25 | EP910ILC-15 | EP910LI-30T |
|---|---|---|---|---|---|---|---|
| Package | 44-pin PLCC | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| Propagation Delay (tPD) | 35 ns | 35 ns | 35 ns | 30 ns | 25 ns | 15 ns | 30 ns |
| Supply Voltage | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) | 5 V (4.75-5.25 V) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Packaging | Tape & Reel | Tube / Tray | Tape & Reel | Tape & Reel | Tube / Tray | Tube / Tray | Tape & Reel |
Bảo phân biệt quan trọng
- Industrial temperature grade for harsh environments (vsEP910LC-35T)
- Tape and Reel packaging for high-volume assembly (vsEP910LI-35)
- Standard 35 ns speed grade for broad application fit (vsEP910ILC-15)
Ghi chú thiết kế
The EP910LI-35T operates from a single 5 V supply (4.75 V to 5.25 V). Decouple VCC with at least one 0.1 uF ceramic capacitor placed within 5 mm of each VCC pin (pins 43 and 44). Add a bulk 10 uF tantalum or aluminum electrolytic capacitor on the 5 V rail near the device to handle transient current during simultaneous output switching. Idle CMOS current consumption is typically 1-5 mA, but dynamic current during high-frequency operation can reach 50-100 mA depending on output loading. Use a regulated linear supply rather than a switching regulator to avoid injecting noise into the EP910's analog-sensitive I/O cells.
The 44-pin PLCC package uses JEDEC-standard surface-mount land pattern with 1.27 mm pin pitch. For socketed deployment, use a low-profile PLCC-44 through-hole socket (e.g., Aries 44-650-10 or equivalent) to enable field replacement without rework. All four GND pins (12, 23, 34) must be connected to a low-impedance ground plane; missing even one GND connection can cause intermittent logic errors due to ground bounce during simultaneous I/O switching. Keep high-speed traces (above 10 MHz) short and routed over a continuous ground plane to minimize EMI and crosstalk.
Do NOT attempt to program the EP910LI-35T with MAX+PLUS II quartus-generated files - the EP910 family uses the legacy programming algorithm (pre-MAX series). Use Altera MAX+PLUS II 10.x or earlier with the appropriate EP910 device support file. Verify programming voltage and timing per the Classic Device Family datasheet - incorrect programming parameters can permanently damage the EPROM cells. For windowed ceramic packages, expose to UV eraser for 20-30 minutes (per datasheet) before reprogramming. Do not exceed maximum I/O source/sink current ratings (typically 4-8 mA per pin) or total package dissipation.
Estimated: At 28.6 MHz fMAX with 12 simultaneously-switching outputs into 50 pF loads, dynamic power dissipation is approximately P = C x V^2 x f x N = 50e-12 x 25 x 28.6e6 x 12 = 429 mW. With PLCC-44 theta_JA of approximately 50 C/W (still air), junction temperature rise is about 21 C above ambient. This is well within the industrial -40C to +85C range, but the design should provide at least 100 mm^2 of copper pour connected to the GND pins to improve thermal dissipation and reduce ground bounce. No external heatsink is required for typical operation.
All I/O pins on the EP910LI-35T are bidirectional with TTL-compatible thresholds (VIL = 0.8 V, VIH = 2.0 V). Unused I/O pins must be programmed as outputs driving LOW or HIGH to avoid floating-input oscillation. For inputs, add a 10 kohm pull-up resistor to VCC to define the default state during power-up before the EPROM is read. Avoid long unterminated traces on clock or high-speed signals - use series damping resistors (22-33 ohm) near the driver if trace length exceeds 50 mm. The 35 ns tPD provides sufficient margin for legacy 8 MHz/16 MHz bus interfaces without additional wait states.
Thông tin tuân thủ
Compliance status for EP910LI-35T not verified in available data - consult Rochester Electronics or Intel PSG product lifecycle documents. Not applicable for AEC-Q100 (logic device without automotive qualification); industrial temperature grade is available via 'LI' suffix but is not equivalent to AEC-Q100 automotive qualification.
