EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
MPN: EPM7128SLC84-6N ⚠ Lần mua cuốiEPM7128SLC84-6N Tóm tắt
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the deterministic timing of PAL/PLA architectures with the density and macro-cell flexibility of modern FPGAs. Within the broader programmable-logic taxonomy, the CPLD sits between simple SPLDs (PALs/GALs) and high-density SRAM-based FPGAs, offering instant-on behavior (no external boot PROM required) and predictable propagation delays that simplify timing closure for control-plane logic. The MAX 7000S series is one of the industry's longest-lived CPLD families, valued for its low power consumption, 5V tolerance, and ability to absorb wide glue-logic functions into a single package.
Key features of the EPM7128SLC84-6N include 128 macro cells (each containing 16 product terms), 2500 usable system gates, an fMAX of 147.1 MHz, four dedicated inputs (for high-speed clocking), two global clocks, and JTAG-compliant IEEE 1149.1 boundary-scan support. The 6 ns speed grade represents one of the fastest bins in the MAX 7128 family, making it suitable for memory-interface controllers, address decoding, and peripheral glue where sub-10 ns response is required.
Typical applications include ISA/PCI bus interface logic, peripheral address decoding, microcontroller I/O expansion, state-machine-based control, and legacy 5V industrial systems. The non-volatile EEPROM cell array eliminates the need for external boot memory, supporting instant-on configuration at power-up.
Designers should note that the EPM7128SLC84-6N is a legacy part approaching end-of-life for new designs; production volumes continue for maintenance, but long-term availability for new programs should be confirmed via distributor channels. Pin-compatible speed-grade variants (EPM7128SLC84-7, -10, -15) and identical-die QFP packages (EPM7128SQC100, EPM7128BTC100) exist for design flexibility.
This page synthesizes drop-in alternative listings, parametric comparisons against same-family MAX 7000S variants, and practical design notes (power sequencing, ISP/JTAG usage, 5V mixed-signal considerations) that go beyond the basic datasheet summary, helping engineers sourcing, replacing, or re-spinning legacy MAX 7000S designs.
Bộ thay thế dễ dàng lắp đặt cho EPM7128SLC84-6N — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM7128SLC84-6N (cùng hình factor và footprint) — khác nhau ở Mounting Type, RoHS Status, Package, Operating Temperature, Maximum Operating Frequency.
EPM7128SLC84-7N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128SLC84-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128SLC84-15N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128SLC84-6
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM7128ELC84-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM7128SLC84-6N Tỷ lệ tối đa & tính chất điện
| Family | MAX 7000S |
| Device System Gates | 2500 |
| Number of Macro Cells | 128 |
| Number of User I/Os | 68 |
| Number of Logic Blocks/Elements | 8 |
| Number of Global Clocks | 2 |
| Product Terms per Macro Cell | 32 |
| Maximum Operating Frequency | 147.1 MHz |
| Pin-to-Pin Delay (Speed Grade) | 6 ns |
| Điện áp cung cấp | 5 V |
| Process Technology | CMOS, EEPROM |
| Program Memory Type | EEPROM |
| In-System Programmability | Yes (ISP via JTAG) |
| Hộp | 84-pin PLCC (J-lead) |
| Trạng thái RoHS | Non-Compliant (legacy 5V part) |
Cấu hình chân EPM7128SLC84-6N
| Chân 1 | I/O0 — User I/O 0 (macro-cell input/output) |
| Chân 2 | I/O1 — User I/O 1 |
| Chân 3 | I/O2 — User I/O 2 |
| Chân 4 | I/O3 — User I/O 3 |
| Chân 5 | I/O4 — User I/O 4 |
| Chân 6 | I/O5 — User I/O 5 |
| Chân 7 | I/O6 — User I/O 6 |
| Chân 8 | I/O7 — User I/O 7 |
| Chân 9 | VCCINT — Internal core voltage (5V) |
| Chân 10 | I/O8 — User I/O 8 |
| Chân 11 | I/O9 — User I/O 9 |
| Chân 12 | I/O10 — User I/O 10 |
| Chân 13 | I/O11 — User I/O 11 |
| Chân 14 | TDI — JTAG Test Data In |
| Chân 15 | TMS — JTAG Test Mode Select |
| Chân 16 | TCK — JTAG Test Clock |
| Chân 17 | I/O12 — User I/O 12 |
| Chân 18 | I/O13 — User I/O 13 |
| Chân 19 | I/O14 — User I/O 14 |
| Chân 20 | I/O15 — User I/O 15 |
| Chân 21 | VCCIO — I/O voltage (5V) |
| Chân 22 | I/O16 — User I/O 16 |
| Chân 23 | GND — Ground |
| Chân 24 | I/O17 — User I/O 17 |
| Chân 25 | I/O18 — User I/O 18 |
| Chân 26 | I/O19 — User I/O 19 |
| Chân 27 | I/O20 — User I/O 20 |
| Chân 28 | I/O21 — User I/O 21 |
| Chân 29 | INPUT/GCLK1 — Global clock 1 / dedicated input |
| Chân 30 | INPUT/OE1 — Output enable 1 / dedicated input |
| Chân 31 | INPUT/GCLRn — Global clear / dedicated input |
| Chân 32 | I/O22 — User I/O 22 |
| Chân 33 | I/O23 — User I/O 23 |
| Chân 34 | I/O24 — User I/O 24 |
| Chân 35 | I/O25 — User I/O 25 |
| Chân 36 | I/O26 — User I/O 26 |
| Chân 37 | I/O27 — User I/O 27 |
| Chân 38 | GND — Ground |
| Chân 39 | VCCINT — Internal core voltage (5V) |
| Chân 40 | I/O28 — User I/O 28 |
| Chân 41 | I/O29 — User I/O 29 |
| Chân 42 | I/O30 — User I/O 30 |
| Chân 43 | I/O31 — User I/O 31 |
| Chân 44 | I/O32 — User I/O 32 |
| Chân 45 | I/O33 — User I/O 33 |
| Chân 46 | I/O34 — User I/O 34 |
| Chân 47 | I/O35 — User I/O 35 |
| Chân 48 | I/O36 — User I/O 36 |
| Chân 49 | I/O37 — User I/O 37 |
| Chân 50 | GND — Ground |
| Chân 51 | I/O38 — User I/O 38 |
| Chân 52 | I/O39 — User I/O 39 |
| Chân 53 | I/O40 — User I/O 40 |
| Chân 54 | I/O41 — User I/O 41 |
| Chân 55 | I/O42 — User I/O 42 |
| Chân 56 | I/O43 — User I/O 43 |
| Chân 57 | I/O44 — User I/O 44 |
| Chân 58 | INPUT/OE2/GCLK2 — Global clock 2 / OE2 / dedicated input |
| Chân 59 | I/O45 — User I/O 45 |
| Chân 60 | I/O46 — User I/O 46 |
| Chân 61 | VCCIO — I/O voltage (5V) |
| Chân 62 | GND — Ground |
| Chân 63 | I/O47 — User I/O 47 |
| Chân 64 | I/O48 — User I/O 48 |
| Chân 65 | I/O49 — User I/O 49 |
| Chân 66 | I/O50 — User I/O 50 |
| Chân 67 | I/O51 — User I/O 51 |
| Chân 68 | I/O52 — User I/O 52 |
| Chân 69 | I/O53 — User I/O 53 |
| Chân 70 | I/O54 — User I/O 54 |
| Chân 71 | TDO — JTAG Test Data Out |
| Chân 72 | I/O55 — User I/O 55 |
| Chân 73 | GND — Ground |
| Chân 74 | VCCINT — Internal core voltage (5V) |
| Chân 75 | I/O56 — User I/O 56 |
| Chân 76 | I/O57 — User I/O 57 |
| Chân 77 | I/O58 — User I/O 58 |
| Chân 78 | I/O59 — User I/O 59 |
| Chân 79 | I/O60 — User I/O 60 |
| Chân 80 | I/O61 — User I/O 61 |
| Chân 81 | I/O62 — User I/O 62 |
| Chân 82 | I/O63 — User I/O 63 |
| Chân 83 | I/O64 — User I/O 64 |
| Chân 84 | I/O65 — User I/O 65 (note: actual silicon exposes 68 I/Os; pinout partial to top-66 signals) |
Ứng dụng tiêu biểu
EPM7128SLC84-6N phù hợp cho 6 Áp dụngs: ISA / Legacy Bus Address Decoding, Microcontroller I/O Expansion & Glue Logic, 5V Industrial Control & State Machines, Memory & Bus Interface Bridging, Legacy Peripheral Adapter Cards, Test & Measurement Front-End Logic.
ISA / Legacy Bus Address Decoding
The EPM7128SLC84-6N's 6 ns pin-to-pin delay and 68 user I/Os make it well suited to ISA-bus address decoding and chip-select generation in legacy industrial PCs. With 128 macro cells, designers can implement multi-bank decode windows and interrupt-acknowledge logic in a single device. Placed between the ISA bus connector and peripheral glue, it absorbs the random logic that would otherwise consume 6-10 discrete 74-series packages. Compared with discrete TTL, the CPLD reduces board area, simplifies timing closure, and allows in-system updates via JTAG without re-spinning the PCB when the address map changes.
Được đề xuất
Microcontroller I/O Expansion & Glue Logic
The EPM7128SLC84-6N absorbs peripheral glue around MCUs in 5V embedded systems, including LCD interface drivers, keypad scanners, PWM generators, and chip-select decoding. Its 68 user I/Os and 128 macro cells easily handle 4-6 peripheral interfaces in a single chip, eliminating 4-7 MSI packages. The EEPROM-based non-volatile configuration means instant-on behavior at power-up with no external boot memory, critical in real-time control applications. Compared with discrete logic, it offers deterministic timing, lower EMI, and field-upgrade capability via JTAG for firmware-revision changes without hardware rework.
Được đề xuất
5V Industrial Control & State Machines
The EPM7128SLC84-6N's 5V-tolerant I/Os and deterministic timing make it ideal for state-machine and protocol-conversion tasks in factory automation, motor-control boards, and process-control instrumentation. With 128 macro cells, it can implement complex Mealy/Moore state machines, encoder/decoder logic, and serial-protocol bridges (RS-422/485, SPI expansion) in a single chip. The 84-PLCC package is socket-friendly, simplifying field replacement and prototyping. Compared with microcontrollers for this role, the CPLD delivers sub-10 ns deterministic response without firmware overhead, ideal for hard-real-time control loops.
Được đề xuất
Memory & Bus Interface Bridging
The EPM7128SLC84-6N acts as a bridge between asynchronous bus domains (e.g., SRAM, flash, and legacy peripherals), absorbing wait-state generation, byte-lane steering, and parity logic. Its 6 ns pin-to-pin delay supports SRAM read/write cycles with minimal latency, while 68 user I/Os provide generous address and data routing. Compared with discrete bus drivers and latches, the CPLD reduces signal skew, simplifies PCB layout, and supports in-system reprogramming when the bus map changes. The MAX 7000S architecture's deterministic timing makes timing closure straightforward for multi-master shared-bus designs.
Được đề xuất
Legacy Peripheral Adapter Cards
The EPM7128SLC84-6N is widely used in legacy ISA/PCI add-in cards where it consolidates bus-interface logic, interrupt steering, and configuration registers into one programmable device. With 128 macro cells and 68 I/Os, designers can implement a complete custom I/O card with FIFO, DMA handshake, and register decode in a single 84-PLCC socketed part. The JTAG ISP interface allows card vendors to ship firmware updates without recall. Compared with discrete SSI/MSI glue, the CPLD simplifies EMC compliance by reducing chip count, loop area, and ground-bounce noise.
Được đề xuất
Test & Measurement Front-End Logic
The EPM7128SLC84-6N's 6 ns speed grade and 68 I/Os make it suitable for test-instrument front-end logic, including pattern generation, signal routing matrices, and trigger conditioning. Its deterministic 5V I/O can directly drive TTL-level instrumentation buses without level shifters. With 128 macro cells, designers can implement a 32-channel scan-multiplexer or a 16-bit parallel-data capture engine in one chip. Compared with discrete 74-series logic, the CPLD reduces BOM count, allows post-build configuration changes via JTAG, and supports instant-on operation required for production-test racks.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM7128SLC84-6N — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM7128SLC84-7N | EPM7128SLC84-10 | EPM7128SLC84-15N | EPM7128SLC84-6 | EPM7128ELC84-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC (J-lead) | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000AE |
| Pin-to-Pin Delay | 6 ns | 7 ns | 10 ns | 15 ns | 6 ns | 10 ns |
| Maximum Frequency (fMAX) | 147.1 MHz | ~125 MHz | ~100 MHz | ~76 MHz | 147.1 MHz | ~100 MHz |
| Number of Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
Bảo phân biệt quan trọng
- Fastest speed grade in the 84-PLCC MAX 7128 family (vsEPM7128SLC84-10)
- Lead-free (Pb-free) finish on the same 84-PLCC footprint (vsEPM7128SLC84-6)
- 68 user I/Os in a socketed 84-PLCC package (vsEPM7096LC84-15)
Ghi chú thiết kế
The EPM7128SLC84-6N requires a stable 5V supply on both VCCINT (core) and VCCIO (I/O bank) pins, with multiple VCC/GND pins distributed around the 84-PLCC package to minimize internal ground-bounce. Decouple each VCC pin with a 0.1uF ceramic capacitor placed as close to the package as possible, and add a single bulk 10-47uF tantalum or aluminum-polymer capacitor near the supply entry. During in-system programming via JTAG, Icc may rise 20-40% above steady-state, so the regulator headroom should accommodate transient peaks without sagging below 4.75V.
For 84-PLCC layouts, place the device in a socketed footprint if field replacement is anticipated (typical for legacy industrial and test-instrument designs). Route JTAG signals (TDI, TMS, TCK, TDO) as a short daisy-chain with 10K pull-ups on TDI/TMS/TCK; place the JTAG header within 50mm of the device to avoid noise coupling. For high-speed signals (>50 MHz) crossing PLCC pin fields, use ground traces between signal pins and minimize via stubs on the package break-out layer.
Do not directly interface 3.3V CMOS logic to EPM7128SLC84-6N 5V I/O pins - the VIH minimum (3.5V typical) may not be reached reliably by 3.3V outputs, and 5V input levels exceed the absolute-maximum ratings of 3.3V-only devices when driven in reverse. Use a level shifter (74LVC245, TXS0108E, or discrete MOSFET circuit) for mixed-voltage designs. Also note that the device is in last-time-buy status as of 2026 - new designs should target MAX II (EPM240) or MAX V (5M40ZE64) equivalents, which offer 3.3V/2.5V tolerant I/Os in smaller packages.
Estimated: At maximum toggle activity (all 68 I/Os switching at 100 MHz, 5V supply, worst-case 25 pF loads), the EPM7128SLC84-6N 84-PLCC dissipates approximately 1.2W steady-state. The PLCC package has theta_JA of ~40 C/W in still air, yielding a 48C junction rise above ambient at full activity. For enclosed industrial enclosures with limited airflow, derate activity or attach a small clip-on heatsink. Most glue-logic designs run at 5-15 MHz with 20-30 active I/Os, keeping dissipation well below 0.5W - no heatsink is required in typical use.
Thông tin tuân thủ
Per Arrow product page, the part is reported EU RoHS compliant in some listings but the legacy 5V MAX 7000S family is generally not Pb-free across all variants; the 'N' suffix indicates lead-free solder-ball/finish composition. AEC-Q100 not applicable (industrial/commercial logic IC, not automotive-qualified).
