ISL26314FVZ - 12-bit 125kSPS 4-CH Differential SAR ADC | Renesas
MPN: ISL26314FVZ ✓ Hoạt độngISL26314FVZ Tóm tắt
What is a SAR ADC? A successive-approximation-register analog-to-digital converter is a sampling ADC architecture that performs one bit-trial per clock cycle using a binary search across an internal capacitive DAC. SAR ADCs are valued for deterministic latency (one conversion = N clock cycles), zero pipeline delay, excellent DC linearity, and low power consumption - they sit in the IC hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. SAR converters are preferred over delta-sigma converters for multiplexed multi-channel sampling where per-channel latency must be deterministic, and over pipeline ADCs when power and simplicity matter more than very high sample rates.
Key features include 4 differential inputs (expandable to 8 single-ended via software), 125 kSPS maximum throughput, ±1 LSB INL (typical), a proprietary input multiplexer with integrated buffer amplifier that reduces external drive requirements, and a wide operating temperature range of -40°C to +125°C. The device also integrates an internal 2.5 V reference (10 ppm/°C typical), an SPI/QSPI/MICROWIRE-compatible serial interface, and a hardware / software shutdown pin that reduces supply current to under 1 µA between conversions.
The ISL26314 is implemented on a low-power CMOS process. An internal charge redistribution DAC combined with the proprietary input multiplexer allows direct connection of high-impedance sensors without external instrumentation amplifiers, simplifying the analog front end. The part is part of a broader pin-compatible family (ISL26310/11/12/13/14/15/19) offering 1, 2, 4, and 8 single-ended and 1, 2, 4 differential channel counts - enabling one PCB layout to scale across product variants.
Typical applications include industrial process control, 4-20 mA loop digitization, multi-cell battery monitoring, programmable logic controller (PLC) analog input modules, weigh scales, and temperature measurement front-ends (RTD/thermocouple with external amplifier).
When designing with this part, note that the input buffer lowers kick-back current into high-source-impedance sensors, but adding an RC anti-alias filter ahead of the input requires careful selection to avoid degrading settling at 125 kSPS. Use the SHDN pin to drop idle channels to microamp-level quiescent current in battery-powered multi-channel systems.
This page synthesizes distributor pricing, same-family pin-compatible drop-in alternatives, and design notes not found in the manufacturer datasheet alone.
Bộ thay thế dễ dàng lắp đặt cho ISL26314FVZ — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ISL26314FVZ (cùng hình factor và footprint) — khác nhau ở Input Type, Number of Input Channels, Package, Interface, Operating Temperature Range.
ISL26314FVZ-T7A
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ISL26314FVZ-T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ISL26312FVZ-T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ISL26311FBZ
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ISL26313FBZ-T7A
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ISL26314FVZ Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bit |
| Sample Rate | 125 kSPS |
| Number of Channels | 4 differential (8 single-ended via mux) |
| ADC Architecture | SAR (Successive Approximation) |
| Input Type | Single-ended / Differential (software-selectable) |
| Analog Supply Voltage (AVDD) | 2.7 V to 5.25 V |
| Digital Supply Voltage (DVDD) | 1.8 V to 3.6 V |
| Supply Current (Full Speed) | 6.4 mW (typical at 3 V) |
| Điện áp tắt | < 1 µA |
| Internal Reference | 2.5 V (10 ppm/°C typical) |
| Giao diện | SPI / QSPI / MICROWIRE-compatible serial |
| Nhiệt độ hoạt động | -40 °C to +125 °C |
| Hộp | 16-pin TSSOP |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | RoHS Compliant (per digchip.com) |
| Lead Free Status | Lead Free (per digchip.com) |
Cấu hình chân ISL26314FVZ
| Chân 1 | AIN0+ — Differential analog input 0, positive |
| Chân 2 | AIN0- — Differential analog input 0, negative |
| Chân 3 | AIN1+ — Differential analog input 1, positive |
| Chân 4 | AIN1- — Differential analog input 1, negative |
| Chân 5 | GND — Ground |
| Chân 6 | REF — Reference voltage input/output (2.5 V internal) |
| Chân 7 | AVDD — Analog supply voltage (2.7 V to 5.25 V) |
| Chân 8 | DVDD — Digital supply voltage (1.8 V to 3.6 V) |
| Chân 9 | GND — Digital ground |
| Chân 10 | CS — Chip select (active low) |
| Chân 11 | SCLK — Serial clock input |
| Chân 12 | SDI — Serial data input (MOSI) |
| Chân 13 | SDO — Serial data output (MISO) |
| Chân 14 | SHDN — Shutdown input (active low) |
| Chân 15 | AIN2+/AIN3+ — Differential analog inputs 2/3 positive (per family datasheet mux) |
| Chân 16 | AIN2-/AIN3- — Differential analog inputs 2/3 negative (per family datasheet mux) |
Ứng dụng tiêu biểu
ISL26314FVZ phù hợp cho 7 Áp dụngs: Industrial Process Control / 4-20 mA Loop Digitization, Multi-Cell Battery Monitoring (BMS), PLC Analog Input Module, Weigh Scale / Bridge Sensor Digitization, Temperature Measurement Front-End (RTD / Thermocouple), Data Acquisition Module / DAS Front-End, Portable / Battery-Powered Instrumentation.
Industrial Process Control / 4-20 mA Loop Digitization
The ISL26314FVZ's 4 differential input channels and 12-bit 125 kSPS throughput make it well-suited to multi-channel industrial process-control digitizers where each differential pair rejects common-mode noise from long sensor cables. Differential inputs handle ±VREF±5 V common-mode signals directly, eliminating the need for an external instrumentation amplifier in many 4-20 mA loop circuits; the integrated 2.5 V reference and buffer amplifier reduce external BOM count. Compared to delta-sigma ADCs, SAR architecture gives deterministic per-channel latency, which matters when the controller runs a multiplexed control loop at fixed update rate.
Được đề xuất
Multi-Cell Battery Monitoring (BMS)
The ISL26314FVZ enables monitoring of up to 4 battery cells (8 cells with software mux pairing) in a battery management system. Differential inputs handle the high common-mode voltage seen when stacked cells share a series string, while the <1 µA shutdown current between conversions extends idle time on battery-powered packs. With 12-bit resolution, the ADC resolves cell voltages to about 1 mV per LSB at typical Li-ion 4.2 V levels, sufficient for coulomb counting and over-voltage/under-voltage protection. SPI/QSPI-compatible serial interface glues directly to common BMS microcontrollers.
Được đề xuất
PLC Analog Input Module
The ISL26314FVZ packs 4 differential channels into a 16-pin TSSOP, allowing a compact 4-channel analog input slice on a PLC backplane. Its 2.7-5.25 V analog and 1.8-3.6 V digital supplies accept the common 24 V -> 5 V/3.3 V PLC rails directly, simplifying power tree design. SPI interface drops onto an isolated SPI barrier (digital isolator) for high-voltage isolation to the PLC CPU. The -40 °C to +125 °C operating range matches industrial control cabinet thermal environments.
Được đề xuất
Weigh Scale / Bridge Sensor Digitization
The ISL26314FVZ's 4 differential inputs accept Wheatstone bridge load-cell outputs directly. Differential signaling rejects 50/60 Hz line noise injected into long cable runs from the scale platform to the indicator. The integrated input buffer lowers kick-back current into the high-impedance bridge, reducing settling time at constant conversion rates and eliminating the external instrumentation amp that bridge digitizers usually require. 12-bit resolution supports commercial weighing scale precision (typically 0.1% FS).
Được đề xuất
Temperature Measurement Front-End (RTD / Thermocouple)
The ISL26314FVZ with external gain stage digitizes RTD or thermocouple signals using its differential inputs. Differential topology rejects ground-loop noise between the sensor and the digitizer, critical for thermocouple measurements where the junction sits at a different ground than the controller. The internal 2.5 V reference can be replaced with an external precision reference for higher absolute accuracy. SPI interface is software-compatible with most microcontroller-based temperature transmitters.
Được đề xuất
Data Acquisition Module / DAS Front-End
The ISL26314FVZ forms the analog front-end of a multi-channel data acquisition system, pairing 4 differential inputs at 125 kSPS aggregate throughput with deterministic SAR latency. The proprietary input multiplexer/buffer amplifier reduces external drive requirements, allowing direct connection to high-impedance sensors without external amplifiers. SPI interface supports multi-ADC daisy-chaining on a single SPI bus - useful when more than 4 channels are needed by stacking multiple ISL26314FVZ devices per CS line.
Được đề xuất
Portable / Battery-Powered Instrumentation
The ISL26314FVZ's 6.4 mW typical power at 3 V and <1 µA shutdown current suit portable handheld instruments. Using the SHDN pin, idle channels drop to microamp-level quiescent current, allowing field instruments to log sensor data over extended battery life. Single 3.3 V operation (AVDD=DVDD) minimizes the power tree. The 16-pin TSSOP is small enough for compact handheld enclosures.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ISL26314FVZ — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ISL26314FVZ-T7A | ISL26314FVZ-T | ISL26312FVZ-T | ISL26311FBZ | ISL26313FBZ-T7A |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 16-pin TSSOP | 16-pin TSSOP (same) | 16-pin TSSOP (same) | 16-pin TSSOP (same) | 16-pin SOIC (16-pin SMT, slightly different footprint) | 16-pin SOIC (16-pin SMT, slightly different footprint) |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate | 125 kSPS | 125 kSPS | 125 kSPS | 125 kSPS | 125 kSPS | 125 kSPS |
| Channel Count (Differential) | 4 differential | 4 differential | 4 differential | 2 differential (-50%) | 1 differential (-75%) | 4 single-ended (0 differential) |
| Internal Reference | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Interface | SPI/QSPI/MICROWIRE | SPI/QSPI/MICROWIRE | SPI/QSPI/MICROWIRE | SPI/QSPI/MICROWIRE | SPI/QSPI/MICROWIRE | SPI/QSPI/MICROWIRE |
| Packaging Form | Tube | Tape & Reel (7-inch) | Tape & Reel | Tape & Reel | Tube | Tape & Reel (7-inch) |
Bảo phân biệt quan trọng
- Highest channel count in same-family pin-compatible family (vsISL26312FVZ-T)
- Differential input topology vs single-ended only (vsISL26313FBZ-T7A)
- Integrated input buffer reduces external drive requirements (vsExternal instrumentation amp + ADC)
Ghi chú thiết kế
Place a 0.1 µF ceramic decoupling capacitor as close as possible to the AVDD pin (pin 7) and another to DVDD (pin 8), plus a 10 µF bulk capacitor on AVDD within 10 mm. Reference pin (pin 6) requires a 0.1 µF + 10 µF decoupling pair to stabilize the internal 2.5 V reference. Use a ground plane on layer 2 to provide low-impedance return paths for the analog inputs; route AVDD/DVDD/REF traces over this plane and avoid routing digital signals (SCLK, SDO) directly over the analog section. Per the ISL26310-26319 family datasheet layout guidance, separate analog and digital ground domains at a single point near the IC to avoid digital switching noise coupling into analog inputs.
Differential input traces (AIN0+/AIN0- through AIN3+/AIN3-) must be routed as a matched-length, balanced pair with constant spacing to preserve common-mode rejection ratio. Keep input traces away from SCLK and SDO digital traces to avoid capacitive coupling; if the layout forces crossings, route at 90 degrees. Place an RC low-pass anti-alias filter ahead of each differential input - typical values are 100 Ω series + 330 pF to ground on each input, giving a ~4.8 MHz cutoff well above the 125 kSPS Nyquist. The proprietary input buffer lowers kick-back current into high-source-impedance sensors, but the external RC must settle within one conversion cycle (8 µs at 125 kSPS) to avoid gain error.
AVDD accepts 2.7 V to 5.25 V and DVDD accepts 1.8 V to 3.6 V. In single-rail 3.3 V systems, AVDD and DVDD may be tied together; per the family datasheet, AVDD must remain within the spec range even during line transients. For noise-sensitive applications, use an LDO (e.g., TPS7A4701) on AVDD instead of a switching regulator to avoid injecting switching noise into the analog supply. The SHDN pin (active low) drops quiescent current to <1 µA when not converting - useful for battery-powered multi-channel systems where the ADC is duty-cycled.
Do not exceed the absolute maximum analog input voltage of AVDD + 0.3 V on any AIN pin - even during fault conditions - or the input ESD diodes will forward-conduct and inject current into the analog supply. Use external TVS diodes or current-limit resistors if the input can exceed this. The internal reference is shared across all input channels; if your application ratiometrically measures against AVDD, configure the ADC for external-reference mode and tie REF to AVDD. The CS pin must be toggled low at the start of each conversion cycle - leaving CS continuously low in SPI mode can cause bus contention in multi-device configurations.
Thông tin tuân thủ
RoHS compliant and lead-free per digchip.com datasheet entry. AEC-Q100 not applicable - this is a general industrial/commercial part, not automotive-grade.