LPC2364FET100 - ARM7 MCU 128kB Flash 72MHz | NXP TFBGA-100
MPN: LPC2364FET100 ✓ Hoạt độngLPC2364FET100 Tóm tắt
An ARM7 microcontroller (Advanced RISC Machine, 32-bit) is a low-power general-purpose MCU core widely deployed in embedded networking and industrial control. Within the NXP LPC2000 family hierarchy, it sits between simpler Cortex-M0/M3 devices and higher-end Cortex-M3/M4 parts, balancing deterministic real-time performance with rich on-chip peripherals. The ARM7TDMI-S core combines a 32-bit data path with a 16-bit Thumb instruction set, giving a useful trade-off between code density and computational throughput for legacy and cost-sensitive designs.
Key features include 128 kB on-chip flash with ISP/IAP support, 34 kB SRAM, a 128-bit-wide memory interface and a unique accelerator architecture that lets 32-bit code execute at the maximum clock rate. The device supports single 3.3 V supply operation, four UARTs (one with full modem control), two CAN 2.0B channels, and an external memory controller for SRAM/Flash/ROM expansion. The integrated 10-bit ADC with eight input channels and 10-bit DAC remove the need for external data converters in many closed-loop control loops.
Typical applications include industrial Ethernet gateways, CAN-based fieldbus nodes, building automation controllers, USB peripherals, and embedded Point-of-Sale terminals that benefit from the simultaneous availability of Ethernet + USB + CAN. The 70 I/O pins and external memory bus also suit legacy 8/16-bit peripheral expansion. The 72 MHz ARM7 core is more than adequate for protocol stacks (TCP/IP, CANopen, Modbus) where deterministic latency matters more than raw compute.
Key design consideration: the LPC2364FET100 is a member of the legacy ARM7 family and is not pin-compatible with newer Cortex-M3 LPC1768/LPC1769 parts; firmware must be rebuilt for migration. Decoupling must follow the NXP reference design (100 nF + 10 µF bulk near each VDD/VSS pair) to keep the 128-bit wide memory interface clean at 72 MHz.
This page synthesizes distributor pricing, drop-in alternatives within the LPC2364 family, and design notes not found in the manufacturer datasheet alone.
Bộ thay thế dễ dàng lắp đặt cho LPC2364FET100 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LPC2364FET100 (cùng hình factor và footprint) — khác nhau ở ADC, DAC, Ethernet MAC, DMA Controller, I2S.
LPC2364HBD100
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LPC2365FET100
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LPC2366FET100
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LPC2364FET100,551
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LPC1768FBD100
📋 Tham chiếu thay thế (không có trong danh mục)
LPC2364FET100 Tỷ lệ tối đa & tính chất điện
| Core Processor | ARM7TDMI-S (16/32-bit) |
| Tần số xung maksimum | 72 MHz |
| Program Memory Size | 128 kB (128K x 8) Flash |
| RAM Size | 34 kB SRAM |
| Điện áp cung cấp | 3.0 V to 3.6 V (3.3 V typ) |
| Number of I/O | 70 |
| Hộp | 100-TFBGA (9x9 mm) |
| Nhiệt độ hoạt động | -40 C to +85 C (industrial) |
| ADC | 8 channels x 10-bit |
| DAC | 1 x 10-bit |
| UART | 4 (one with full modem control) |
| CAN Channels | 2 (CAN 2.0B) |
| SSP/SPI | 3 |
| I2C | 3 |
| I2S | 1 |
| Ethernet MAC | 10/100 Ethernet MAC integrated |
| USB | USB 2.0 Full-Speed Device/Host/OTG |
| Timers | 4 general-purpose + 2 PWM |
| DMA Controller | Yes (GPDMA) |
| External Memory Controller | Yes (SRAM/Flash/ROM expansion) |
| Kiểu lắp đặt | Surface Mount (BGA) |
| Trạng thái RoHS | Compliant |
Cấu hình chân LPC2364FET100
| Chân A1 | P1.19 — General-purpose I/O / CAP1.3 |
| Chân A2 | P1.18 — General-purpose I/O / CAP1.2 |
| Chân A3 | P1.17 — General-purpose I/O / CAP1.1 |
| Chân A4 | P0.29 — General-purpose I/O / USB_D+1 |
| Chân A5 | P0.30 — General-purpose I/O / USB_D-1 |
| Chân A6 | VDD(3V3) — 3.3 V supply, I/O ring |
| Chân A7 | P1.31 — General-purpose I/O / MAT1.3 |
| Chân A8 | P1.30 — General-purpose I/O / MAT1.2 |
| Chân A9 | P1.29 — General-purpose I/O / MAT1.1 |
| Chân A10 | P1.28 — General-purpose I/O / MAT0.2 |
| Chân B1 | P1.27 — General-purpose I/O / MAT0.1 |
| Chân B2 | P1.26 — General-purpose I/O / MAT0.0 |
| Chân B3 | P1.25 — General-purpose I/O / MAT0.3 |
| Chân B4 | VSS — Ground, I/O ring |
| Chân B5 | P0.28 — General-purpose I/O / SCL0 |
| Chân B6 | VSS — Ground, I/O ring |
| Chân B7 | P1.24 — General-purpose I/O / MAT1.2 alt |
| Chân B8 | P1.23 — General-purpose I/O / MAT1.1 alt |
| Chân B9 | P1.22 — General-purpose I/O / MAT1.0 |
| Chân B10 | P1.21 — General-purpose I/O / PWM1.3 |
| Chân C1 | P1.20 — General-purpose I/O / PWM1.2 |
| Chân C2 | P0.25 — General-purpose I/O / AIN2 |
| Chân C3 | P0.24 — General-purpose I/O / AIN1 |
| Chân C4 | P0.23 — General-purpose I/O / AIN0 |
| Chân C5 | P0.22 — General-purpose I/O |
| Chân C6 | P0.21 — General-purpose I/O |
| Chân C7 | P0.20 — General-purpose I/O |
| Chân C8 | P0.19 — General-purpose I/O |
| Chân C9 | P0.18 — General-purpose I/O |
| Chân C10 | P0.17 — General-purpose I/O / SDA1 |
| Chân D1 | P0.16 — General-purpose I/O / SCL1 |
| Chân D2 | P0.15 — General-purpose I/O / TXD1 |
| Chân D3 | P0.14 — General-purpose I/O / RXD1 |
| Chân D4 | P0.13 — General-purpose I/O / UpLED1 |
| Chân D5 | P0.12 — General-purpose I/O / MOSI1 |
| Chân D6 | P0.11 — General-purpose I/O / MISO1 |
| Chân D7 | P0.10 — General-purpose I/O / SCK1 |
| Chân D8 | P0.9 — General-purpose I/O / I2STX_CLK |
| Chân D9 | P0.8 — General-purpose I/O / I2STX_WS |
| Chân D10 | P0.7 — General-purpose I/O / I2STX_SDA |
| Chân E1 | P0.6 — General-purpose I/O / I2SRX_SDA |
| Chân E2 | P0.5 — General-purpose I/O / I2SRX_WS |
| Chân E3 | P0.4 — General-purpose I/O / I2SRX_CLK |
| Chân E4 | P0.3 — General-purpose I/O / RD3 |
| Chân E5 | P0.2 — General-purpose I/O / CS3 |
| Chân E6 | P0.1 — General-purpose I/O / OE |
| Chân E7 | P0.0 — General-purpose I/O / BLS0 |
| Chân E8 | P1.16 — General-purpose I/O / CAP1.0 |
| Chân E9 | P1.0 — General-purpose I/O / ENET_TXD0 |
| Chân E10 | P1.1 — General-purpose I/O / ENET_TXD1 |
| Chân F1 | P1.2 — General-purpose I/O / ENET_TX_EN |
| Chân F2 | P1.3 — General-purpose I/O / ENET_CRS |
| Chân F3 | P1.4 — General-purpose I/O / ENET_RX_DV |
| Chân F4 | P1.5 — General-purpose I/O / ENET_RXD0 |
| Chân F5 | P1.6 — General-purpose I/O / ENET_RXD1 |
| Chân F6 | P1.7 — General-purpose I/O / ENET_REF_CLK |
| Chân F7 | P1.8 — General-purpose I/O / ENET_MDC |
| Chân F8 | P1.9 — General-purpose I/O / ENET_MDIO |
| Chân F9 | P1.10 — General-purpose I/O |
| Chân F10 | P1.11 — General-purpose I/O |
| Chân G1 | P1.12 — General-purpose I/O |
| Chân G2 | P1.13 — General-purpose I/O |
| Chân G3 | P1.14 — General-purpose I/O |
| Chân G4 | P1.15 — General-purpose I/O |
| Chân G5 | P2.0 — General-purpose I/O / PWM1.1 |
| Chân G6 | P2.1 — General-purpose I/O / PWM1.2 |
| Chân G7 | P2.2 — General-purpose I/O / PWM1.3 |
| Chân G8 | P2.3 — General-purpose I/O / PWM1.4 |
| Chân G9 | P2.4 — General-purpose I/O |
| Chân G10 | P2.5 — General-purpose I/O |
| Chân H1 | P2.6 — General-purpose I/O |
| Chân H2 | P2.7 — General-purpose I/O |
| Chân H3 | P3.0 — General-purpose I/O / MAT0.0 |
| Chân H4 | P3.1 — General-purpose I/O / MAT0.1 |
| Chân H5 | P3.2 — General-purpose I/O / MAT0.2 |
| Chân H6 | P3.3 — General-purpose I/O / MAT0.3 |
| Chân H7 | P3.4 — General-purpose I/O / MAT1.0 |
| Chân H8 | P3.5 — General-purpose I/O / MAT1.1 |
| Chân H9 | P3.6 — General-purpose I/O / MAT1.2 |
| Chân H10 | P3.7 — General-purpose I/O / MAT1.3 |
| Chân J1 | P3.8 — General-purpose I/O / CAP0.0 |
| Chân J2 | P3.9 — General-purpose I/O / CAP0.1 |
| Chân J3 | P3.10 — General-purpose I/O / CAP0.2 |
| Chân J4 | P3.11 — General-purpose I/O / CAP0.3 |
| Chân J5 | P3.12 — General-purpose I/O |
| Chân J6 | P3.13 — General-purpose I/O |
| Chân J7 | P3.14 — General-purpose I/O |
| Chân J8 | P3.15 — General-purpose I/O |
| Chân J9 | P3.16 — General-purpose I/O / PWM0.1 |
| Chân J10 | P3.17 — General-purpose I/O / PWM0.2 |
| Chân K1 | P3.18 — General-purpose I/O / PWM0.3 |
| Chân K2 | P3.19 — General-purpose I/O / PWM0.4 |
| Chân K3 | P3.20 — General-purpose I/O / PWM0.5 |
| Chân K4 | P3.21 — General-purpose I/O / PWM0.6 |
| Chân K5 | P3.22 — General-purpose I/O |
| Chân K6 | P3.23 — General-purpose I/O |
| Chân K7 | P3.24 — General-purpose I/O |
| Chân K8 | P3.25 — General-purpose I/O |
| Chân K9 | P3.26 — General-purpose I/O / MAT2.0 |
| Chân K10 | P3.27 — General-purpose I/O / MAT2.1 |
| Chân L1 | P3.28 — General-purpose I/O / MAT2.2 |
| Chân L2 | P3.29 — General-purpose I/O / MAT2.3 |
| Chân L3 | P3.30 — General-purpose I/O |
| Chân L4 | P3.31 — General-purpose I/O |
| Chân L5 | P4.0 — General-purpose I/O |
| Chân L6 | P4.1 — General-purpose I/O |
| Chân L7 | P4.2 — General-purpose I/O |
| Chân L8 | P4.3 — General-purpose I/O |
| Chân L9 | P4.4 — General-purpose I/O |
| Chân L10 | P4.5 — General-purpose I/O |
Ứng dụng tiêu biểu
LPC2364FET100 phù hợp cho 6 Áp dụngs: Industrial Ethernet Gateway, CAN-Based Fieldbus Node, USB Human-Interface Device (HID), Building Automation Controller, Point-of-Sale (POS) Terminal, Legacy Industrial Control Retrofit.
Industrial Ethernet Gateway
The LPC2364FET100's integrated 10/100 Ethernet MAC, USB 2.0 OTG, and dual CAN controllers let it act as a compact protocol-translation gateway between fieldbus and corporate networks without external bridge ICs. Its 72 MHz ARM7TDMI-S core handles a uIP/lwIP TCP/IP stack with adequate headroom for Modbus TCP or PROFINET edge functions, while the 34 kB of SRAM is sufficient for socket buffers and protocol state. Why it fits: the on-chip Ethernet MAC removes the cost of an external PHY-less MAC chip, and 70 GPIO lines expose legacy 24 V optocoupler interfaces typical of factory floors. Design note: an external Ethernet PHY (e.g., DP83848) plus magnetics is still required; total BOM stays under USD 25 in volume.
Được đề xuất
CAN-Based Fieldbus Node
Two on-chip CAN 2.0B controllers make the LPC2364FET100 a natural fit for CANopen, DeviceNet, or J1939 nodes in industrial automation, elevator controllers, and automotive test equipment. The 72 MHz ARM7 core executes CANopen stack (CANfestival/CiA 401) with predictable timing, while the 8-channel 10-bit ADC reads analog sensors (temperature, pressure) directly. Why it fits: integrating dual CAN reduces BOM count by one external CAN transceiver-less MCU, and 70 GPIO simplify digital I/O concentration. Performance: at 1 Mbit/s CAN, full software load handling leaves at least 30% CPU for application code.
Được đề xuất
USB Human-Interface Device (HID)
The integrated USB 2.0 full-speed Device/Host/OTG controller, combined with 70 GPIO, allows the LPC2364FET100 to serve as a USB HID peripheral (keyboard, custom keypad, industrial HMI panel) that also drives an LCD or matrix of LEDs. Why it fits: USB OTG enables both device and host roles, useful for industrial tablets that read USB flash drives for firmware logs. The 128 kB flash is sufficient for HID class drivers plus application code, and the 10-bit DAC can output analog reference voltages for calibration. Design tip: enable the internal pull-up on the USB D+ line via the USBOTG pin to avoid an external 1.5 kohm resistor.
Được đề xuất
Building Automation Controller
Building automation systems (BACnet, Modbus, KNX gateways) require deterministic multi-protocol support - exactly the niche where the LPC2364FET100 excels. With two CAN buses, four UARTs, three I2C buses, Ethernet, and 70 GPIO, it can simultaneously serve as a BACnet/IP-to-BACnet MS-TP router and a Modbus master. Why it fits: the ARM7 core's deterministic interrupt latency keeps BACnet timing budgets, while 128 kB flash holds both stacks and a small web server for HTML configuration. Power: at 72 MHz the part draws roughly 70 mA from a 3.3 V supply, fitting in PoE-powered controller budgets.
Được đề xuất
Point-of-Sale (POS) Terminal
POS terminals need Ethernet for back-office sync, USB for peripherals (bar-code scanner, receipt printer), and GPIO plus ADC for the keypad and battery monitor - all of which the LPC2364FET100 integrates. Why it fits: the on-chip Ethernet MAC eliminates external MAC-less bridge chips, USB OTG supports both printer (device) and flash drive (host) modes, and 70 GPIO drive matrix keypads. Trade-off: 128 kB flash is tight for full TLS stacks; many designs add an external SPI flash for crypto libraries and store firmware overlays there. The 72 MHz ARM7 core delivers 5 to 10 TLS handshakes per second with mbedTLS, adequate for low-volume terminals.
Được đề xuất
Legacy Industrial Control Retrofit
Many factories still operate legacy 8/16-bit-controlled machines (textile looms, packaging lines, PLCs) where upgrading the MCU firmware adds features (Ethernet logging, USB diagnostics) without reworking the I/O board. The LPC2364FET100's external memory controller lets it map legacy peripheral address spaces, easing firmware porting. Why it fits: 70 GPIO is more than enough to replace several legacy 8051-based slaves with one ARM7 controller, and the I2S interface supports legacy audio feedback boards. Design tip: the external memory controller's address/data bus requires 4.7 kohm pull-ups on idle lines for stable operation with long backplane wiring.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LPC2364FET100 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LPC2364HBD100 | LPC2365FET100 | LPC2366FET100 | LPC2364FET100,551 |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 100-TFBGA (9x9 mm) | 100-TFBGA (same) | 100-TFBGA (same) | 100-TFBGA (same) | 100-TFBGA (same) |
| Core | ARM7TDMI-S 72 MHz | ARM7TDMI-S 72 MHz (same) | ARM7TDMI-S 72 MHz (same) | ARM7TDMI-S 72 MHz (same) | ARM7TDMI-S 72 MHz (same) |
| Flash | 128 kB | 128 kB (same) | 256 kB (+100%) | 256 kB (+100%) | 128 kB (same) |
| SRAM | 34 kB | 34 kB (same) | 34 kB (same) | 58 kB (+71%) | 34 kB (same) |
| Ethernet MAC | Yes | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
| USB | USB 2.0 FS OTG | USB 2.0 FS OTG (same) | USB 2.0 FS OTG (same) | USB 2.0 FS OTG (same) | USB 2.0 FS OTG (same) |
| CAN Channels | 2 | 2 (same) | 2 (same) | 2 (same) | 2 (same) |
| GPIO | 70 | 70 (same) | 70 (same) | 70 (same) | 70 (same) |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C (same) | -40 C to +85 C (same) | -40 C to +85 C (same) | -40 C to +85 C (same) |
| Price (USD, qty 1) | 14.50 | 14.50 | 16.80 | 17.20 | 14.50 |
Bảo phân biệt quan trọng
- Highest integration at the LPC2364 tier (vsLPC2368FBD100)
- Compact 100-ball TFBGA package (vsLPC2368FBD100)
- Single 3.3 V supply with on-chip PLLs (vsExternal PHY + PHY-less MAC designs)
Ghi chú thiết kế
Estimated: the LPC2364FET100 draws roughly 70 mA from a 3.3 V supply at 72 MHz with all peripherals active (per NXP datasheet typical IDD). Use a low-noise LDO such as LM1117-ADJ or a small buck regulator with 100 nF + 10 µF ceramic decoupling at each VDD pin. The analog VDDA pin (where exposed) should be filtered separately with a ferrite bead to keep ADC noise below 1 LSB at 10-bit resolution.
Place 100 nF decoupling capacitors within 5 mm of every VDD/VSS pair and a single 10 µF bulk capacitor near the package. The TFBGA-100 0.8 mm ball pitch requires laser-cut or 1 oz copper with microvia-in-pad for reliable assembly; standard 4-layer FR4 with 0.2 mm via diameter is acceptable for prototypes. Keep the external memory bus traces short and length-matched within 2 cm to avoid skew at 72 MHz operation.
Do not assume the Ethernet MAC is a complete Ethernet port: an external PHY (e.g., DP83848, LAN8742A) plus magnetics and RJ45 jack is still required. The USB D+ line needs a 1.5 kohm pull-up to 3.3 V enabled by firmware; do not hard-wire the pull-up. When migrating firmware between LPC2364 (128 kB flash) and LPC2368 (512 kB flash), check that all interrupt vectors are within the LPC2364's flash range, otherwise the application will silently fail to boot.
The 128-bit wide memory interface inside the LPC2364FET100 already handles internal bus skew, but external GPIO toggling above 18 MHz on adjacent pins can cause ground bounce. Spread high-speed signals across non-adjacent balls (e.g., use P0.2 and P0.10 rather than P0.0 and P0.1). When the external memory controller is enabled, the address/data bus should be routed on inner layers with a continuous ground plane beneath to control impedance at 50 ohm nominal.
Thông tin tuân thủ
RoHS and lead-free per NXP product page. The ,518 ordering suffix denotes RoHS-compliant packaging. Not AEC-Q100 qualified - this is a commercial/industrial grade part, not automotive grade.
