LTC2165IUK - 16-Bit 125Msps Low Power ADC | Analog Devices
MPN: LTC2165IUK ✓ Hoạt độngLTC2165IUK Tóm tắt
An ADC, or analog-to-digital converter, is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes at a specified sampling rate. Pipelined ADCs like the LTC2165 employ a multi-stage sub-ADC architecture that interleaves conversions to achieve high sample rates while maintaining low power and small die area. They sit within the broader hierarchy of data converters, which includes successive-approximation (SAR), delta-sigma, and flash ADCs, and are the workhorse of high-speed signal acquisition systems.
Key features of the LTC2165IUK include ultralow 0.07 ps RMS aperture jitter for accurate undersampling of IF frequencies, selectable LVDS/CMOS output modes for flexible board interfacing, an internal 2.5 V reference, and a maximum power dissipation of 314 mW at full 125 Msps operation. The pipelined architecture introduces a fixed conversion latency but supports continuous streaming with no cycle loss in either the CMOS or LVDS mode.
The LTC2165IUK shares an identical pinout with the lower-speed LTC2164 (105 Msps) and LTC2163 (80 Msps) variants, allowing a single PCB layout to serve multiple performance targets. Digital outputs can be configured as full-rate CMOS, multiplexed CMOS for low-pin-count interfaces, or LVDS for high-noise-immunity backplanes. An internal reference and flexible input common-mode range simplify the analog front-end design.
Typical applications include multiband, multimode cellular base-station receivers, software-defined radio (SDR) front ends, low-power handheld test instruments, medical imaging receivers, and spectrum analysis systems. The 125 Msps sampling rate combined with 16-bit resolution allows direct digitization of signals at IF frequencies such as 70 MHz or 140 MHz, simplifying receiver signal chains.
Designers should pay attention to analog input network design: a wideband transformer or differential amplifier driver is recommended to preserve SFDR at high input frequencies, and a low-jitter sampling clock must be provided through a CMOS or LVPECL source to maintain the rated SNR. Decoupling must include a low-inductance 1 uF and 0.1 uF pair near the supply pins.
This page synthesizes distributor pricing, pin-compatible speed-grade alternatives within the LTC2163/2164/2165 family, and practical design notes not found concisely in the manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho LTC2165IUK — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2165IUK (cùng hình factor và footprint) — khác nhau ở Input Type, Operating Temperature Range, Package, Reference, RoHS Status.
LTC2164IUK#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2163IUK#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2165CUK#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2165IUK Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 16 bit |
| Number of Channels | 1 |
| Tỷ lệ lấy mẫu | 125 Msps |
| Architecture | Pipelined |
| Input Type | Single-ended / Differential |
| Phạm vi điện áp đầu vào | 1 Vp-p / 2 Vp-p |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Power Dissipation | 314 mW (max) |
| Output Interface | Parallel CMOS / LVDS (selectable) |
| Reference | Internal 2.5 V (or external) |
| Supply Voltage (Digital) | 1.8 V (typ) |
| Supply Voltage (Analog) | 1.8 V (typ) |
| Khoảng nhiệt độ hoạt động | -40C to +85C (I grade) |
| Hộp | 48-QFN (7x7 mm, UK suffix) |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant (#PBF suffix) |
Cấu hình chân LTC2165IUK
| Chân 1 | GND — Ground (analog and digital ground connect at single point) |
| Chân 2 | AIN+ — Positive analog input |
| Chân 3 | AIN- — Negative analog input (differential) |
| Chân 4 | VCM — Common-mode voltage output |
| Chân 5 | REFH — Reference high pin, decouple to ground |
| Chân 6 | REFL — Reference low pin, decouple to ground |
| Chân 7 | VREF — Internal 2.5V reference bypass |
| Chân 8 | REFP — Positive reference decoupling |
| Chân 9 | REFN — Negative reference decoupling |
| Chân 10 | SENSE — Reference select / ground sense |
| Chân 11 | GND — Ground |
| Chân 12 | VDD — Analog 1.8V supply |
| Chân 13 | GND — Ground |
| Chân 14 | VDD — Analog 1.8V supply |
| Chân 15 | GND — Ground |
| Chân 16 | VDD — Analog 1.8V supply |
| Chân 17 | ENC+ — Encoder (clock) positive input |
| Chân 18 | ENC- — Encoder (clock) negative input |
| Chân 19 | GND — Ground |
| Chân 20 | D13 — Data output bit 13 |
| Chân 21 | D14 — Data output bit 14 |
| Chân 22 | D15 — Data output bit 15 (MSB) |
| Chân 23 | OGND — Output driver ground |
| Chân 24 | OVDD — Output driver supply (1.8V) |
| Chân 25 | D12 — Data output bit 12 |
| Chân 26 | D11 — Data output bit 11 |
| Chân 27 | D10 — Data output bit 10 |
| Chân 28 | D9 — Data output bit 9 |
| Chân 29 | D8 — Data output bit 8 |
| Chân 30 | OGND — Output driver ground |
| Chân 31 | OVDD — Output driver supply |
| Chân 32 | D7 — Data output bit 7 |
| Chân 33 | D6 — Data output bit 6 |
| Chân 34 | D5 — Data output bit 5 |
| Chân 35 | D4 — Data output bit 4 |
| Chân 36 | D3 — Data output bit 3 |
| Chân 37 | D2 — Data output bit 2 |
| Chân 38 | D1 — Data output bit 1 |
| Chân 39 | D0 — Data output bit 0 (LSB) |
| Chân 40 | OGND — Output driver ground |
| Chân 41 | OVDD — Output driver supply |
| Chân 42 | OF — Overflow / out-of-range flag |
| Chân 43 | MODE — Output mode (CMOS full-rate, CMOS demux, LVDS) |
| Chân 44 | CS — Chip select / SPI configuration enable |
| Chân 45 | SDI — Serial data input for SPI programming |
| Chân 46 | SCK — Serial clock for SPI programming |
| Chân 47 | RAND — Randomizer enable / dither control |
| Chân 48 | GND — Ground / exposed pad |
Ứng dụng tiêu biểu
LTC2165IUK phù hợp cho 6 Áp dụngs: Multiband Cellular Base Station Receivers, Software-Defined Radio (SDR) Front Ends, Low-Power Handheld Test Instruments, Medical Imaging Receiver Chains, Spectrum Analyzer IF Digitization, Phased Array Radar / EW Receivers.
Multiband Cellular Base Station Receivers
The LTC2165IUK directly digitizes wideband IF signals in 3G/4G/5G multiband base-station receivers, eliminating discrete mixer-and-filter downconversion stages. Its 76.8 dB SNR and 90 dB SFDR preserve modulation accuracy for high-order QAM and OFDM carriers, while 0.07 ps RMS aperture jitter enables undersampling of carriers above 100 MHz IF without SNR degradation. Drawing 314 mW at full 125 Msps, it fits dense radio cards where thermal density matters, and the 48-QFN (7x7 mm) UK footprint eases board layout alongside DSPs and FPGAs.
Được đề xuất
Software-Defined Radio (SDR) Front Ends
In SDR platforms where receivers are software-retargeted across many waveforms, the LTC2165IUK's 125 Msps sample rate and 16-bit resolution provide headroom for both narrowband and wideband signals on a single hardware platform. Its aperture jitter of 0.07 ps RMS allows direct sampling of L-band and HF-band signals below the ADC input bandwidth, simplifying analog filtering. LVDS output mode reduces common-mode digital switching noise in dense SDR boards where FPGA placement leaves little analog isolation, and the 48-QFN footprint eases fanout routing.
Được đề xuất
Low-Power Handheld Test Instruments
Handheld spectrum analyzers, oscilloscopes, and field-portable RF instruments benefit from the LTC2165IUK's 76.8 dB SNR and 314 mW dissipation, which balances measurement fidelity against battery runtime. Industrial -40C to +85C operation allows deployment in outdoor environments such as tower-top PIM analyzers or drive-test scanners, while the 90 dB SFDR ensures that large-signal blocker resilience is maintained without spurious responses that would mask weak signals. A wide 1-2 Vp-p programmable input range simplifies front-end attenuator networks in portable instruments.
Được đề xuất
Medical Imaging Receiver Chains
Ultrasound and MRI receiver channels digitize processed IF signals at tens of MHz; the LTC2165IUK's 125 Msps sample rate captures 50 MHz IF bandwidth with 16-bit dynamic range, supporting image detail in low-contrast diagnostics. Its differential 2 Vp-p input range handles direct IF outputs from low-noise variable-gain amplifiers, and the selectable CMOS output mode simplifies interface to legacy DSP subsystems used in cart-based ultrasound machines. Low aperture jitter is critical for harmonic imaging where phase coherence across receives is essential.
Được đề xuất
Spectrum Analyzer IF Digitization
Wideband spectrum analyzers and swept-tuned measurement receivers often employ an IF-digitization architecture where the final stage converts the last 70-140 MHz IF into digital domain. The LTC2165IUK's 16-bit resolution and 76.8 dB SNR exceed typical spectrum analyzer noise-floor requirements, while 90 dB SFDR enables the >80 dBc dynamic range specified for compliance-test instruments. LVDS output mode preserves signal integrity over the backplane to a host FPGA at full 125 Msps, and the 48-QFN UK package occupies minimal board area in modular spectrum analyzer cards.
Được đề xuất
Phased Array Radar / EW Receivers
Electronically-steered phased-array radar and electronic-warfare receivers route digitized element signals to FPGA processors for beamforming; the LTC2165IUK's combination of 125 Msps sample rate and 16-bit resolution allows each element to capture 60+ MHz instantaneous bandwidth per channel. Low 0.07 ps RMS aperture jitter preserves accurate phase information across the array, which directly determines beam pointing and sidelobe levels. Selectable LVDS output is well suited to high-element-count arrays where many ADCs feed a single FPGA over short, controlled-impedance traces.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2165IUK — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2164IUK#PBF | LTC2163IUK#PBF | LTC2165CUK#PBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7 mm, UK) | 48-QFN (7x7 mm, UK) - same | 48-QFN (7x7 mm, UK) - same | 48-QFN (7x7 mm, UK) - same |
| Sampling Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit |
| SNR | 76.8 dB | 76.8 dB | 76.8 dB | 76.8 dB |
| SFDR | 90 dB | 90 dB | 90 dB | 90 dB |
| Aperture Jitter | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | 0C to +70C (C grade) |
| Max Power Dissipation | 314 mW | 275 mW (approx at 105 Msps) | 240 mW (approx at 80 Msps) | 314 mW |
| 1ku List Price | $97.55 | $87.55 (approx) | $73.50 (approx) | $97.55 |
Bảo phân biệt quan trọng
- Highest sample rate in the pin-compatible LTC2163/2164/2165 family (vsLTC2164IUK#PBF)
- Industrial temperature grade -40C to +85C for harsh environments (vsLTC2165CUK#PBF)
- Ultralow 0.07 ps RMS aperture jitter enables direct IF sampling (vsLTC2163IUK#PBF)
Ghi chú thiết kế
Drive the AIN+/AIN- differential inputs through a wideband RF transformer (e.g., Mini-Circuits ADT1-1WT) or a low-distortion differential amplifier such as the ADA4927. Source impedance matching to 100 ohms differential is critical for SFDR at input frequencies above 70 MHz. The SENSE pin must be tied to VREF for internal reference operation. ESTIMATED: per Analog Devices' 'Transformer-Coupled Differential Input' applications, this preserves >80 dB SFDR at 100 MHz IF. Use a low-jitter clock source; any clock jitter adds directly to aperture-jitter-limited SNR.
The 48-QFN UK package uses an exposed pad that must be soldered to a continuous ground plane for thermal dissipation and electrical return. Analog (VDD) and digital output driver (OVDD) supplies should each have a 1 uF ceramic in parallel with a 0.1 uF capacitor placed within 5 mm of the pins. Separate analog and digital ground planes should be stitched only at the exposed pad. ESTIMATED: per Analog Devices QFN layout guidelines, this arrangement reduces digital coupling into the analog front end and preserves the datasheet's 90 dB SFDR.
Do not leave the SENSE pin floating - tie to VREF for internal reference, or to GND for external reference. Driving the ENC+/ENC- clock inputs with long, poorly-terminated traces >5 cm will degrade SNR due to clock jitter multiplication. When using LVDS output mode, ensure 100-ohm differential termination at the receiver; mismatched termination generates reflections that appear as spurious tones in the ADC output spectrum. ESTIMATED: per the LTC2165 datasheet timing section, clock jitter above 0.5 ps RMS will visibly impact SNR.
Thông tin tuân thủ
RoHS compliant per #PBF suffix designation. Lead-free finish (SnAgCu) confirmed. Halogen-free status not explicitly stated in the verified data; flagged as [DATA_NEEDED]. AEC-Q100 not applicable for industrial-grade non-automotive ADC. REACH compliance status confirmed via Analog Devices product page environment section.
