LTC2164IUK - 16-Bit 105Msps Low Power ADC | Analog Devices
MPN: LTC2164IUK ✓ Hoạt độngLTC2164IUK Tóm tắt
What is a pipelined ADC? A pipelined ADC is a multi-stage converter architecture that resolves a high-frequency analog input by passing it through a cascade of low-resolution flash stages interleaved with sample-and-hold amplifiers and digital error correction. Each stage performs a coarse conversion, computes a residue, and feeds the residue to the next stage. Within the broader taxonomy, the LTC2164 sits in the chain: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined ADCs dominate the >10 Msps, >12-bit converter market because they deliver the best trade-off among speed, resolution, and power consumption.
Key features of the LTC2164IUK include 105 Msps sampling rate, 16-bit resolution, 76.8 dB SNR, 90 dB SFDR, 0.07 ps RMS jitter, an integrated high-bandwidth differential sample-and-hold front end, selectable CMOS/LVDS output modes, and an internal reference (with optional external reference override). The part operates from a single 1.8 V analog supply plus a separate digital output supply (1.8 V CMOS mode, or 2.5 V LVDS mode), and consumes only 150 mW typical at full speed with CMOS outputs.
The 48-QFN (7x7) package is thermally efficient and exposes a die-attach pad that must be soldered to a low-impedance ground pour. Internal register programmability is accessed via a 3-wire SPI-compatible serial interface. The architecture supports both single-ended and differential analog inputs, which simplifies front-end design across multiple baseband and IF topologies. Together these characteristics make the LTC2164 a flexible ADC for software-defined radio, LTE/4G base stations, medical imaging front ends, and high-speed data acquisition.
Typical applications include communications basestations (LTE, WiMAX, GSM/EDGE), medical imaging ultrasound front ends, high-speed test and measurement instrumentation (digitizers, oscilloscopes, spectrum analyzers), IF undersampling in software-defined radio, and radar/LIDAR signal chains.
When designing with the LTC2164IUK, pay close attention to analog input common-mode bias, clock duty-cycle stability, and the LVDS/CMOS output supply choice. Decoupling must include dedicated low-ESL/ESR capacitors placed within 2 mm of each supply pin. The exposed pad (EP) is the primary thermal path and must be soldered to a continuous ground plane for rated performance.
This page synthesizes distributor pricing, verified drop-in alternatives, and practical design guidance not found on a single distributor listing or in the bare datasheet, providing engineers with an actionable evaluation summary.
Bộ thay thế dễ dàng lắp đặt cho LTC2164IUK — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2164IUK (cùng hình factor và footprint) — khác nhau ở Input Type, Package, Resolution, RoHS Status, Operating Temperature Range.
LTC2163IUK
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2165IUK
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2174IUKG-14
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →LTC2159IUK
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2207CUK#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2164IUK Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 16 bit |
| Number of Input Channels | 1 |
| Sampling Rate (Max) | 105 Msps |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended (selectable) |
| SNR (Typical) | 76.8 dB |
| SFDR (Typical) | 90 dB |
| Aperture Jitter (RMS) | 0.07 ps |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage (CMOS mode) | 1.8 V |
| Digital Supply Voltage (LVDS mode) | 2.5 V |
| Power Consumption (Typical, 105 Msps, CMOS) | 150 mW |
| Output Format | CMOS or LVDS (selectable) |
| Hộp | 48-QFN (7x7 mm) with exposed pad |
| Kiểu lắp đặt | Surface Mount |
| Khoảng nhiệt độ hoạt động | -40C to +85C (industrial) |
| Reference | Internal (external override optional) |
| Configuration Interface | SPI-compatible serial |
| Trạng thái RoHS | Compliant |
| Số chân | 48 |
Cấu hình chân LTC2164IUK
| Chân 1 | AIN+ — Differential analog input positive |
| Chân 2 | AIN- — Differential analog input negative |
| Chân 3 | CM — Common-mode bias output (drive to analog input) |
| Chân 4 | REF — Internal reference decoupling / external reference input |
| Chân 5 | SENSE — Reference mode select |
| Chân 6 | OGND — Output buffer ground |
| Chân 7 | OVDD — Output supply voltage |
| Chân 8 | DNC — Not connected (reserved) |
| Chân 9 | D0_0 — LVDS/CMOS data output bit 0 (LSB lane 0) |
| Chân 10 | D0_1 — LVDS/CMOS data output bit 1 (lane 0) |
| Chân 11 | D0_2 — LVDS/CMOS data output bit 2 (lane 0) |
| Chân 12 | D0_3 — LVDS/CMOS data output bit 3 (lane 0) |
| Chân 13 | D0_4 — LVDS/CMOS data output bit 4 (lane 0) |
| Chân 14 | D0_5 — LVDS/CMOS data output bit 5 (lane 0) |
| Chân 15 | D0_6 — LVDS/CMOS data output bit 6 (lane 0) |
| Chân 16 | D0_7 — LVDS/CMOS data output bit 7 (lane 0) |
| Chân 17 | D0_8 — LVDS/CMOS data output bit 8 (lane 0) |
| Chân 18 | D0_9 — LVDS/CMOS data output bit 9 (lane 0) |
| Chân 19 | OGND — Output buffer ground |
| Chân 20 | OVDD — Output supply voltage |
| Chân 21 | D0_10 — LVDS/CMOS data output bit 10 (lane 0) |
| Chân 22 | D0_11 — LVDS/CMOS data output bit 11 (lane 0) |
| Chân 23 | D0_12 — LVDS/CMOS data output bit 12 (lane 0) |
| Chân 24 | D0_13 — LVDS/CMOS data output bit 13 (lane 0) |
| Chân 25 | D0_14 — LVDS/CMOS data output bit 14 (lane 0) |
| Chân 26 | D0_15 — LVDS/CMOS data output bit 15 (MSB, lane 0) |
| Chân 27 | OGND — Output buffer ground |
| Chân 28 | OVDD — Output supply voltage |
| Chân 29 | CLKOUT- — Differential clock output negative |
| Chân 30 | CLKOUT+ — Differential clock output positive |
| Chân 31 | OGND — Output buffer ground |
| Chân 32 | OVDD — Output supply voltage |
| Chân 33 | DNC — Not connected (reserved) |
| Chân 34 | OE — Output enable (active high) |
| Chân 35 | CS — SPI chip select (active low) |
| Chân 36 | SCK — SPI serial clock |
| Chân 37 | SDI — SPI serial data input |
| Chân 38 | SDO — SPI serial data output |
| Chân 39 | GND — Digital ground |
| Chân 40 | AVDD — Analog 1.8 V supply |
| Chân 41 | AVDD — Analog 1.8 V supply |
| Chân 42 | GND — Analog ground |
| Chân 43 | GND — Analog ground |
| Chân 44 | CLK- — Differential clock input negative |
| Chân 45 | CLK+ — Differential clock input positive |
| Chân 46 | AVDD — Analog 1.8 V supply |
| Chân 47 | GND — Analog ground |
| Chân 48 | GND — Analog ground |
Ứng dụng tiêu biểu
LTC2164IUK phù hợp cho 6 Áp dụngs: Communications Basestations (LTE / WiMAX / 4G / 5G), Medical Imaging (Ultrasound Front Ends), Software-Defined Radio (SDR) and IF Sampling, High-Speed Test and Measurement Instrumentation, Radar and LIDAR Signal Processing, Industrial Non-Destructive Testing (NDT) and Ultrasound Inspection.
Communications Basestations (LTE / WiMAX / 4G / 5G)
The LTC2164IUK's 76.8 dB SNR and 90 dB SFDR at 105 Msps directly meet the dynamic range required for digital-IF downconversion in LTE, WiMAX, and 4G/5G basestation receivers. Its 0.07 ps RMS aperture jitter preserves EVM when undersampling high-IF carriers, while its 150 mW typical power budget eases thermal design in compact RRH modules. The selectable CMOS or LVDS outputs allow direct connection to FPGAs or ASICs without external level translation. Typical deployment places the LTC2164 between a SAW filter and an FPGA-based baseband processor, sampling at 61.44 or 122.88 Msps for LTE compatibility.
Được đề xuất
Medical Imaging (Ultrasound Front Ends)
Ultrasound beamforming systems require ADCs with very low jitter to preserve phase coherence across transducer channels. The LTC2164IUK's 0.07 ps RMS aperture jitter ensures that phase errors between 16, 32, or 64 parallel channels remain well below 1 degree at frequencies up to 15 MHz, critical for harmonic imaging and Doppler processing. Its 76.8 dB SNR supports dynamic range above 70 dB needed for clinical ultrasound contrast resolution. The 48-QFN (7x7) footprint is compact enough for high-density probe electronics where each square millimeter counts. Designers typically pair the LTC2164 with a low-noise LNA (e.g. AD8099) and a differential driver such as the ADA4932.
Được đề xuất
Software-Defined Radio (SDR) and IF Sampling
Software-defined radio architectures depend on ADCs that can undersample high IF frequencies while preserving noise performance. The LTC2164IUK's 0.07 ps RMS jitter and wide analog input bandwidth allow direct sampling of IF signals in the 70-140 MHz range at 105 Msps, eliminating a complete downconversion stage and reducing BOM cost. The integrated SPI port enables software-tunable gain, offset, and test-pattern injection for production calibration. This part is commonly paired with Xilinx or Altera FPGAs implementing digital downconversion, with the LTC2164's LVDS mode minimizing EMI on long PCB traces to the FPGA.
Được đề xuất
High-Speed Test and Measurement Instrumentation
Automated test equipment (ATE), oscilloscopes, and spectrum analyzers demand ADCs with high linearity and SFDR to resolve small signals in the presence of large tones. The LTC2164IUK's 90 dB SFDR provides a usable spur-free dynamic range well above 80 dB even at full speed, enabling 16-bit effective ENOB at 30 MHz input. Its differential input simplifies interfacing with active probes and AC-coupled front ends, while the 1.8 V analog supply integrates cleanly with modern low-voltage FPGA/ASIC signal chains. Designers building digitizers up to 100 MHz instantaneous bandwidth find the LTC2164 a flexible workhorse.
Được đề xuất
Radar and LIDAR Signal Processing
Pulsed radar and LIDAR systems rely on fast, low-jitter ADCs to capture narrow returns with high time-domain accuracy. The LTC2164IUK's 105 Msps sample rate and 0.07 ps jitter translate to a timing resolution well below 100 ps after interpolation, which is critical for centimeter-class range precision. Its single-channel differential input supports the high-impedance front-end typical of avalanche photodiode or PIN receiver chains. The 48-QFN package is small enough to mount directly behind the optical receiver, minimizing analog trace length and preserving SNR in the 70 dB range.
Được đề xuất
Industrial Non-Destructive Testing (NDT) and Ultrasound Inspection
Industrial ultrasonic flaw detectors and NDT equipment use wideband ADCs to digitize high-frequency acoustic echoes from metals, composites, and welds. The LTC2164IUK at 105 Msps can directly sample transducer frequencies up to 30 MHz, supporting modern phased-array probes with multiple focal laws. Its high SFDR prevents spurious responses from masking small defect echoes, while its industrial temperature rating (-40C to +85C) suits outdoor and shop-floor environments. The exposed pad of the 48-QFN provides mechanical rigidity when mounted on carrier boards inside portable NDT scanners.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2164IUK — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2163IUK | LTC2165IUK | LTC2174IUKG-14 | LTC2159IUK | LTC2207CUK#PBF |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 14 bit | 16 bit | 16 bit |
| Sampling Rate (Max) | 105 Msps | 80 Msps | 125 Msps | 105 Msps | 20 Msps | 105 Msps |
| Output Format | CMOS or LVDS | CMOS or LVDS | CMOS or LVDS | CMOS or LVDS | CMOS or LVDS | CMOS |
Bảo phân biệt quan trọng
- Best SNR-to-power ratio in the 105 Msps 16-bit class (vsLTC2207CUK#PBF)
- Programmable SPI configuration interface (vsLTC2207CUK#PBF)
- Compatible with the LTC2163/LTC2165 family for design reuse (vsLTC2174IUKG-14)
- Lower aperture jitter than legacy 16-bit ADCs (vsLTC2159IUK)
Ghi chú thiết kế
The LTC2164IUK requires two separate low-noise supplies: AVDD (1.8 V analog) and OVDD (1.8 V CMOS or 2.5 V LVDS). Use a star-ground architecture with separate LDOs (e.g., LT3042 for analog, LT3045 for digital) feeding each rail. Decouple each AVDD pin with a 1 uF X7R ceramic within 2 mm of the pin plus a 10 uF bulk cap; OVDD pins require similar treatment. Estimated: total quiescent power is ~150 mW at 105 Msps with CMOS outputs - plan thermal relief accordingly.
The 48-QFN (7x7) package dissipates up to 250 mW under worst-case load. Solder the exposed pad (EP) to a continuous ground plane spanning at least 1 square inch of 2 oz copper to keep junction temperature rise below 15C. Do not rely on the EP being optional - omitting it will degrade SNR and may violate the absolute maximum junction temperature. Use a 4-layer PCB with dedicated ground/power planes for best thermal and electrical performance.
Route the analog inputs (AIN+, AIN-) as a 100-ohm differential pair matched within 2 mm. Keep digital output traces (D0_0 through D0_15, CLKOUT+/-, FRAME) routed on a separate PCB layer, away from analog signals. The CLK+/- input must be driven by a low-jitter clock source (jitter < 0.5 ps RMS) - clock jitter directly adds to aperture jitter and degrades SNR at high input frequencies. Place a 100-ohm differential termination resistor at the ADC end of the CLK trace.
Common pitfalls include: (1) driving the analog input with a single-ended source - use a differential driver like ADA4932-2; (2) leaving the SENSE pin floating - tie it to AVDD for internal reference, or to GND for external; (3) failing to set the OE pin high during operation; (4) driving CLK with a non-50%-duty-cycle source, which causes gain error; (5) ignoring the input common-mode voltage (CM) pin output - it must be buffered and applied to the input driver reference. Estimated: each pitfall above can reduce SNR by 3-10 dB if unaddressed.
Thông tin tuân thủ
RoHS and REACH compliant per Analog Devices product page. Industrial temperature grade -40C to +85C. Not AEC-Q100 qualified (not intended for automotive under-the-hood applications).