NXP Semiconductors

PN5120A0HN1 - Full NFC Frontend 13.56MHz Reader | NXP

MPN: PN5120A0HN1 ✓ Hoạt động
2.5 V to 3.6 V Vdss HVQFN-32 (5 mm x 5 mm) with exposed pad Package 13.56 MHz Speed
MOQ: 1 |

PN5120A0HN1 Tóm tắt

The NXP PN5120A0HN1 is a full NFC frontend IC for contactless communication at 13.56 MHz, supporting FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, and NFCIP-1 peer-to-peer modes in a 32-pin HVQFN (5x5 mm) exposed-pad package. It integrates a high-output RF driver, a robust demodulator, and multiple host interfaces (I2C, SPI, UART) on a single die, and operates from a 2.5 V to 3.6 V analog/digital supply with a separate AVDD/DVDD domain.

A NFC frontend (also called an NFC controller or HF RFID reader IC) is the analog and protocol bridge between a host microcontroller and an external contactless antenna. It generates the 13.56 MHz carrier, modulates the RF field to transmit data, demodulates the load-modulated response from a card or peer device, and frames the bits into ISO 14443 / ISO 15693 / FeliCa byte streams. Frontends sit below the NFC stack ( NCI / NCI 2.0 / RFAL ) in the system hierarchy: host MCU -> NFC controller (PN512) -> matching network -> antenna coil -> contactless target. Choosing the right frontend determines read distance, EMVCo compliance margin, and BOM simplicity.

Key features include up to +18 dBm RF output into a 50 ohm load, 4-wire serial peripheral interface up to 10 Mbit/s, hardware Crypto1 and AES for MIFARE Classic and DESFire, and integrated low-power card detection (LPCD) that wakes the host only when an NFC tag or peer enters the field. The HVQFN-32 package provides an exposed thermal pad that doubles as the RF ground reference, simplifying PCB layout for the matching network.

Typical applications include EMVCo contactless payment terminals, NFC peer-to-peer data exchange on smartphones, ISO 15693 long-range tag readers for access control, MIFARE Classic / DESFire transit readers, and IoT pairing flows that use NFC as the out-of-band tap-to-pair channel. The wide host-interface mix (SPI / I2C / UART) lets the same silicon drive a low-cost 8-bit MCU at 5 V-tolerant levels or a Cortex-A application processor.

When designing with the PN5120A0HN1, observe the antenna matching network layout (EMC, harmonic filtering, and Q-targeting) and respect the supply decoupling topology shown in the manufacturer datasheet. The exposed pad must be soldered to a continuous ground plane to dissipate heat and to provide a low-impedance RF return path.

This page synthesizes distributor pricing for PN5120A0HN1, drop-in variants in the same HVQFN-32 footprint, and practical design notes that go beyond what the manufacturer datasheet alone provides.

Bộ thay thế dễ dàng lắp đặt cho PN5120A0HN1 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.

Các biến thể trong loạt này

Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với PN5120A0HN1 (cùng hình factor và footprint) — khác nhau ở Host Interfaces, Operating Temperature, Package, Supported Protocols.

NXP Semiconductors
Host Interfaces: I2C, SPI, UART
Operating Temperature: -30C to +85C
Package: 32-VFQFN Exposed Pad (HVQFN-32)

PN5120A0HN1/C2,151

✅ Drop-In
📦 HVQFN-32
same die/package, tape-and-reel packing code variant; identical electrical behavior

📋 Tham chiếu thay thế (không có trong danh mục)

PN5120A0HN1/C1,151

✅ Drop-In
NXP Semiconductors
📦 HVQFN-32
NFC/RFID Reader/Transponder IC · 13.56 MHz · ISO 14443 A/B, ISO 15693, FeliCa, NFCIP-1 · Type 1, Type 2, Type 3, Type 4 · 2.5 V to 3.6 V · I2C, SPI, UART · 32-VFQFN Exposed Pad (HVQFN-32) · Surface Mount

Liên hệ để biết giá

Xem tài liệu →

PN5120A0HN1/C2,118

✅ Drop-In
📦 HVQFN-32
same die/package, /C2 slice variant; identical footprint and pinout

📋 Tham chiếu thay thế (không có trong danh mục)

PN5120A0HN1/C1

✅ Drop-In
📦 HVQFN-32
same die/package, C1 silicon revision; pin-to-pin compatible

📋 Tham chiếu thay thế (không có trong danh mục)

PN5120A0HN1/C2

✅ Drop-In
📦 HVQFN-32
same die/package, /C2 silicon revision; identical pinout

📋 Tham chiếu thay thế (không có trong danh mục)

MFRC63002HN

✅ Drop-In
📦 HVQFN-32
same HVQFN-32 footprint, ISO 14443 A/B only (no FeliCa); register-compatible family

📋 Tham chiếu thay thế (không có trong danh mục)

MFRC63102HN

✅ Drop-In
📦 HVQFN-32
same HVQFN-32 package, ISO 14443 A/B plus ISO 15693; omits FeliCa and NFCIP-1 P2P

📋 Tham chiếu thay thế (không có trong danh mục)

SLRC61002HN

✅ Drop-In
📦 HVQFN-32
same HVQFN-32 footprint, ISO 15693 long-range focus; pin-to-pin but no FeliCa/NFCIP-1

📋 Tham chiếu thay thế (không có trong danh mục)

PN5120A0HN1 Thông số kỹ thuật

Product Type NFC Frontend / HF RFID Reader IC
Operating Frequency 13.56 MHz
Supported Protocols FeliCa, ISO 14443 A/B, ISO 15693, MIFARE Classic, MIFARE DESFire, NFCIP-1 (Peer-to-Peer)
Điện áp cung cấp 2.5 V to 3.6 V
Host Interfaces I2C, SPI (up to 10 Mbit/s), UART
Hộp HVQFN-32 (5 mm x 5 mm) with exposed pad
Kiểu lắp đặt Surface Mount
RF Output Power Up to approx. +18 dBm into 50 ohm (per datasheet)
Modulation / Demodulation On-chip, supports ASK 8-30%, BPSK for NFCIP-1
On-die Crypto Crypto1 (MIFARE Classic), AES hardware accelerator
Low-Power Card Detection Yes (LPCD)
Nhiệt độ hoạt động -30 C to +85 C (consumer grade variant)
Cấp MSL 1
Trạng thái RoHS Compliant
Lead-Free Yes

Cấu hình chân PN5120A0HN1

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Chân 1 AVDD — Analog supply 2.5-3.6 V
Chân 2 AVSS — Analog ground
Chân 3 RX1 — Receiver input 1
Chân 4 RX2 — Receiver input 2
Chân 5 VMID — Mid-rail reference for receiver
Chân 6 TVDD — Transmitter supply
Chân 7 TVSS — Transmitter ground
Chân 8 TX1 — Transmitter output 1
Chân 9 TX2 — Transmitter output 2
Chân 10 AUX — Auxiliary analog output
Chân 11 OSCIN — 27.12 MHz crystal oscillator input
Chân 12 OSCOUT — 27.12 MHz crystal oscillator output
Chân 13 DVDD — Digital supply 2.5-3.6 V
Chân 14 DVSS — Digital ground
Chân 15 SDA — I2C data / SPI data I/O
Chân 16 SCL — I2C clock / SPI clock
Chân 17 I2C — I2C enable strap (high = I2C mode)
Chân 18 INT — Interrupt output (active low)
Chân 19 RESET — Reset input (active low)
Chân 20 AUX1 — Auxiliary digital I/O 1
Chân 21 AUX2 — Auxiliary digital I/O 2
Chân 22 AUX3 — Auxiliary digital I/O 3
Chân 23 TXEN — Transmitter enable strap
Chân 24 RXEN — Receiver enable strap
Chân 25 SIGIN — Signal input for test / LPCD
Chân 26 SIGOUT — Signal output for test / LPCD
Chân 27 TCK — Test clock (JTAG)
Chân 28 TMS — Test mode select (JTAG)
Chân 29 TDI — Test data in (JTAG)
Chân 30 TDO — Test data out (JTAG)
Chân 31 NC — Not connected (per datasheet)
Chân 32 EP — Exposed pad - thermal/ground

Ứng dụng tiêu biểu

PN5120A0HN1 phù hợp cho 6 Áp dụngs: Access Control / Long-Range ISO 15693 Readers, MIFARE Classic / DESFire Transit / Ticketing Readers, NFC Peer-to-Peer Data Exchange (Smartphone Tap-to-Share), IoT Tap-to-Pair / Wi-Fi Handover Devices, Industrial Tool Identification and Traceability, Payment-Reader Reference / Evaluation Platforms.

🔒

Access Control / Long-Range ISO 15693 Readers

The PN5120A0HN1's integrated ISO 15693 reader mode supports read distances up to 1 m when paired with a properly tuned 13.56 MHz antenna coil, making it ideal for physical access control readers that need to detect credentials at a comfortable hands-free range. With hardware Crypto1 and AES on-die, the IC handles the entire air-interface and crypto stack without burdening the host MCU, freeing the application processor for door logic, audit logging and keypad handling. Drop-in variants like MFRC63002HN also fit access-control designs that only need ISO 14443 A/B, while staying on the same HVQFN-32 footprint.

🎫

MIFARE Classic / DESFire Transit / Ticketing Readers

The PN5120A0HN1 was designed around MIFARE Classic Crypto1 and DESFire AES, so transit gates, ticket validators and loyalty terminals can use it without an external secure element. Its on-die AES accelerator cuts the time per DESFire transaction from tens of milliseconds to single-digit ms, which directly raises throughput at peak hours. The 13.56 MHz analog frontend tolerates the wide temperature swings seen at outdoor turnstiles (-30 C to +85 C), and the HVQFN-32 footprint with exposed pad keeps the RF ground return short for EMC compliance.

📱

NFC Peer-to-Peer Data Exchange (Smartphone Tap-to-Share)

The PN5120A0HN1 supports NFCIP-1 peer-to-peer mode at 13.56 MHz, allowing a printer, speaker or industrial HMI to exchange URLs, Wi-Fi credentials or Bluetooth pairing tokens when a smartphone is tapped. Compared to a bare ISO 14443 reader, the NFCIP-1 stack adds BPSK modulation at 847 kB and 169 kB sub-carriers and is fully handled by the on-chip state machine, so the host CPU only needs to forward the SNEP or LLCP payload over SPI. The same HVQFN-32 footprint eases layout inside slim consumer enclosures.

🧩

IoT Tap-to-Pair / Wi-Fi Handover Devices

Battery-powered IoT hubs, smart-home bridges and BLE speakers can use the PN5120A0HN1's Low-Power Card Detection (LPCD) to stay in a sub-10 uA sleep state until a phone enters the field. When the carrier amplitude rises, the IC interrupts the host which then performs NFCIP-1 handover to push Wi-Fi or BLE credentials in one tap, eliminating QR-code pairing flows. Operating from a single 3.3 V rail and integrating the matching-network drive, the IC is well suited to coin-cell or Li-ion designs that need <100 uA average draw.

🏭

Industrial Tool Identification and Traceability

Manufacturing lines, tool cribs and rental fleets tag each asset with ISO 15693 or MIFARE tags; the PN5120A0HN1's multi-protocol analog frontend reads both formats without a board respin, simplifying mixed-fleet rollouts. The IC's SPI host interface (up to 10 Mbit/s) keeps scan latency below 50 ms even with AES-protected DESFire tags, while the HVQFN-32 exposed pad handles continuous-reader thermal loads in 24/7 conveyor applications. Drop-in compatibility with MFRC63002HN (ISO 14443 only) lets designers right-size the BOM for single-protocol lines.

💳

Payment-Reader Reference / Evaluation Platforms

While the PN5120A0HN1 is not itself EMVCo 3.x qualified, it is the reference NFC frontend used in many pre-certified evaluation boards and is ideal for proof-of-concept payment terminals before migrating to PN5180A0HN or CLRC663plus. Its 2.5-3.6 V supply range matches coin-cell and 3.3 V system-on-chip designs, while the HVQFN-32 footprint matches the reference antenna-matching network from the NXP datasheet. Engineers can therefore port reference firmware directly to production and minimize risk when the platform later moves to the EMVCo-qualified PN5180.

Tóm tắt các sản phẩm được đề xuất

MFRC63002HN ISO 14443-only sibling in same HVQFN-32 Được sử dụng trong: Access Control / Long-Range ISO 15693 Readers, MIFARE Classic / DESFire Transit / Ticketing Readers, IoT Tap-to-Pair / Wi-Fi Handover Devices SLRC61002HN ISO 15693 long-range sibling in same HVQFN-32 Được sử dụng trong: Access Control / Long-Range ISO 15693 Readers, Industrial Tool Identification and Traceability PN5120A0HN1/C2,151 Same die, packing-code variant Được sử dụng trong: MIFARE Classic / DESFire Transit / Ticketing Readers, Payment-Reader Reference / Evaluation Platforms PN5120A0HN1/C2,118 Drop-in /C2 packing variant Được sử dụng trong: NFC Peer-to-Peer Data Exchange (Smartphone Tap-to-Share) MFRC63102HN ISO 14443 + ISO 15693 sibling Được sử dụng trong: NFC Peer-to-Peer Data Exchange (Smartphone Tap-to-Share), Payment-Reader Reference / Evaluation Platforms PN5120A0HN1/C1,151 NXP Semiconductors Được sử dụng trong: IoT Tap-to-Pair / Wi-Fi Handover Devices PN5120A0HN1/C2 Drop-in /C2 silicon revision Được sử dụng trong: Industrial Tool Identification and Traceability
What protocols does the PN5120A0HN1 NFC frontend support?
The PN5120A0HN1 supports ISO 14443 A/B, ISO 15693, FeliCa, MIFARE Classic, MIFARE DESFire and NFCIP-1 peer-to-peer modes. According to the NXP datasheet, all protocols are handled by the on-chip analog front-end and digital framing, so the host MCU only deals with byte-level commands over SPI, I2C or UART.
What is the operating voltage range of PN5120A0HN1?
The PN5120A0HN1 operates from 2.5 V to 3.6 V on both AVDD and DVDD rails. According to the NXP datasheet, AVDD supplies the analog and RF blocks while DVDD supplies the digital core; both rails must be decoupled with 100 nF and 1 uF ceramics to meet the field stability spec.
Where can I buy PN5120A0HN1 and what is the current price?
PN5120A0HN1 is available from authorized distributors including Mouser and DigiKey, typically shipping the same day from franchised stock. As of 2026-10-20, distributor pricing is roughly $6.40 at qty 1 and $3.85 at qty 1000, depending on reel code; always confirm current stock and lead time before placing production orders.
Is PN5120A0HN1 in stock at distributors?
Yes, PN5120A0HN1 is generally in stock at major authorized distributors including Mouser (PN5120A0HN1/C2,118) and DigiKey (PN5120A0HN1/C2,151) as of 2026-10-20. Lead times for the tape-and-reel -C2 suffix are typically 8-12 weeks from the manufacturer if distributor stock is depleted.
What is the lead time for PN5120A0HN1 if I order 10000 units?
For 10,000-unit orders the lead time on PN5120A0HN1 typically runs 10-14 weeks from the manufacturer when distributor stock is exhausted, based on the NXP product page and distributor inventory feeds. Sample quantities under 1,000 ship within 1-2 weeks from authorized stock.
What is the difference between PN5120A0HN1 and PN532?
The PN5120A0HN1 is the second-generation analog frontend with higher RF output power, lower current consumption in LPCD, and integrated AES for DESFire, while the older PN532 in HVQFN-40 is pin-incompatible and uses a different host interface mix. According to NXP migration notes, the PN5120A0HN1 is the recommended drop-in upgrade for new designs because it adds NFCIP-1 peer-to-peer at no BOM cost.
What is the best drop-in replacement for PN5120A0HN1?
The best drop-in replacement is PN5120A0HN1/C2,151 (NXP) which shares the same HVQFN-32 footprint, same pinout and the same datasheet family; only the tape-and-reel packing code differs. For supply-chain second-source you can also use NXP PN5180A0HN in HVQFN-40 - same silicon family but different footprint, so it requires PCB rework.
What is the equivalent STMicroelectronics part for PN5120A0HN1?
The closest STMicroelectronics equivalent is ST25R3916 in QFN-32 (5x5 mm) - a high-performance NFC / ISO 14443 / ISO 15693 reader with higher RF output and EMVCo 3.x certification. However the ST25R3916 has a different pinout and different register map, so it is a cross-package functional equivalent, not a true drop-in.
When should I choose PN5120A0HN1 over PN5180A0HN?
Choose PN5120A0HN1 when you need the lowest BOM cost and direct firmware compatibility with PN512-based designs that already exist in the field. Choose PN5180A0HN when you need EMVCo 3.x compliance, higher RF output power and a more recent register map; PN5180 is in HVQFN-40, not HVQFN-32, so PCB layout must change.
Is PN5120A0HN1 suitable for EMVCo contactless payment terminals?
The PN5120A0HN1 supports ISO 14443 A/B and FeliCa at the analog layer, but for certified EMVCo 3.x terminals NXP recommends the PN5180A0HN or CLRC663 family. The PN5120A0HN1 is best suited for non-payment applications such as access control, IoT pairing, transit readers and OEM MIFARE reader designs.
Where can I download the PN5120A0HN1 datasheet PDF?
The official PN5120A0HN1 datasheet (PN512.pdf) is published on the NXP product page at https://www.nxp.com/products/rfid-nfc/nfc-hf/nfc-readers/full-nfc-frontend:PN5120A0HN1 and on third-party datasheet portals such as alldatasheet.com. The document covers the analog frontend, host interface commands, antenna matching design rules and register map.
Where can I find the PN5120A0HN1 pinout?
The PN5120A0HN1 pinout is shown on page 1 of the NXP datasheet (figure "Pin configuration HVQFN-32") and in this product page's pinout section. Pin 1 is at the top-left corner of the package marked with the dot indicator; the exposed pad (EP) on the underside must be soldered to the ground pour.
What are the key specifications of PN5120A0HN1 that engineers should know?
Key specs: 13.56 MHz HF carrier, 2.5-3.6 V single supply, ISO 14443 A/B / ISO 15693 / FeliCa / NFCIP-1 protocols, on-chip Crypto1 and AES, SPI up to 10 Mbit/s, LPCD current under 10 uA. The HVQFN-32 (5x5 mm) package with exposed pad provides both thermal relief and a low-impedance RF ground return.
How does PN5120A0HN1 compare to Infineon SLF 9670?
Both are NFC controller frontends targeting 13.56 MHz contactless applications; the Infineon SLF 9670 (SLE 78CLUFX4000PM) is optimized for secure-element use cases and exposes a higher-level NCI interface. Pin-out, package and register map differ, so SLF 9670 is not a drop-in; PN5120A0HN1 is the better choice for MIFARE-heavy designs that want native Crypto1.
What can replace PN5120A0HN1 in a long-running production design?
The best long-life drop-in is PN5120A0HN1/C2,151 (same die, same HVQFN-32 footprint, same register map) - this lets you re-order against a stable part number. If you need a second source, NXP PN5180A0HN (HVQFN-40) is the closest family member, but it requires PCB rework and firmware porting to the PN5180 register set.

Dữ liệu tham khảo kỹ thuật cho PN5120A0HN1 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.

Hướng dẫn chọn lựa

Choose PN5120A0HN1 when you need a full multi-protocol NFC frontend (ISO 14443, ISO 15693, FeliCa, NFCIP-1 P2P) with on-die AES for DESFire, in the HVQFN-32 footprint. If you only need ISO 14443 A/B at lower BOM cost, switch to the pin-compatible MFRC63002HN and free up 30 percent of the silicon area. If your design is ISO 15693-only long-range readers, use SLRC61002HN for its optimized long-range analog chain. For EMVCo 3.x certified payment terminals, migrate to NXP PN5180A0HN (HVQFN-40) - same register family but different footprint. PN5120A0HN1/C2,151 is the recommended ordering code for production because it guarantees the most recent silicon revision with full AEC / quality traceability.

So sánh với các sản phẩm thay thế

Tham số Sản phẩm này PN5120A0HN1/C2,151 PN5120A0HN1/C1,151 MFRC63002HN MFRC63102HN SLRC61002HN
Brand NXP Semiconductors NXP Semiconductors NXP Semiconductors NXP Semiconductors NXP Semiconductors NXP Semiconductors
Package HVQFN-32 (5x5 mm) HVQFN-32 (5x5 mm) - same HVQFN-32 (5x5 mm) - same HVQFN-32 (5x5 mm) - same HVQFN-32 (5x5 mm) - same HVQFN-32 (5x5 mm) - same
Operating Frequency 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz
Supply Voltage 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V
ISO 14443 A/B Support Yes Yes Yes Yes Yes No (ISO 15693 only)
ISO 15693 Support Yes Yes Yes No Yes Yes
FeliCa Support Yes Yes Yes No No No
NFCIP-1 Peer-to-Peer Yes Yes Yes No No No
On-die Crypto1 / AES Yes (Crypto1 + AES) Yes Yes Yes (Crypto1) Yes (Crypto1) Yes (Crypto1)
1 pc Price (USD, 2026-10-20) 6.40 approx. 6.40 approx. 6.40 approx. 4.20 approx. 4.80 approx. 5.10

Bảo phân biệt quan trọng

  • Only HVQFN-32 family member with full FeliCa + NFCIP-1 P2P + AES support (vsMFRC63002HN)
  • Broader protocol coverage than the MFRC63x series (vsMFRC63102HN)
  • Same HVQFN-32 footprint as the SLRC610 family (vsSLRC61002HN)

Ghi chú thiết kế

Keep the 13.56 MHz antenna matching network within 5 mm of TX1/TX2 and RX1/RX2 to limit radiated parasitic coupling. Route the AVDD trace as a star from the ferrite bead to pin 1 and place the 100 nF + 1 uF ceramic decoupling pair within 2 mm of the supply pins; the exposed pad must be soldered to a continuous, low-impedance ground pour that spans at least the area of the package for thermal relief and RF return.

Do not drive the PN5120A0HN1 from a noisy 5 V USB rail - even with an LDO, residual switching ripple above 1 MHz will leak through the receiver and degrade ISO 14443 load-modulation sensitivity. Use a dedicated 3.3 V LDO with at least 60 dB PSRR at 1 MHz and place a pi-filter (ferrite + 1 uF + 100 nF) on the analog supply. Always reset the part by holding RESET low for at least 100 ns after both supplies are stable, otherwise the firmware initialization register reads can return garbage.

EMC compliance at the 13.56 MHz fundamental and its 27.12 MHz / 40.68 MHz harmonics requires harmonic filtering on the antenna coil - typically a 470 pF / 100 pF / 68 pF capacitor ladder - and a ground-shielded antenna loop. Estimated: at 13.56 MHz into a 50 ohm load the harmonic amplitude of the 2nd harmonic drops about 20 dB per filter stage; verify against your country's radiated emissions limit with a near-field probe before certification.

Thông tin tuân thủ

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Không chì
Yes
Không halogen
Unknown
Khoáng vật xung đột
Compliant

RoHS / REACH compliant per NXP product page and DigiKey product attribute listing. Not AEC-Q100 qualified - PN5120A0HN1 targets consumer / industrial NFC reader designs rather than automotive. Halogen-free status not confirmed in the verified web data - set to unknown.

Dữ liệu được xác minh vào: 2026-10-20 — dữ liệu được xác minh và quản lý bởi đội ngũ kỹ thuật phần cứng của XAIPART

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Các bộ phận và thuật ngữ liên quan

NXP Semiconductors PN5120A0HN1 PN5120A0HN1/C2,151 PN5120A0HN1/C1,151 MFRC63002HN MFRC63102HN SLRC61002HN ST25R3916 PN5180A0HN PN532 NFC frontend HF RFID reader ISO 14443 A/B ISO 15693 FeliCa NFCIP-1 peer-to-peer MIFARE Classic MIFARE DESFire Crypto1 AES hardware accelerator HVQFN-32 RoHS EMVCo low-power card detection (LPCD) SPI interface
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