What ChipAgents and NVIDIA's Build-A-Chip-Bench means for autonomous RTL-to-GDS tooling

Reported by Semiconductor Digest on 2026-10-15. Summarized and analyzed by XAIPART Editorial.

What happened

ChipAgents, an agentic AI platform for semiconductor engineering, introduced Build-A-Chip-Bench, a benchmark developed in collaboration with NVIDIA to measure whether AI agents can carry a digital chip-design task from specification through physical implementation and verified GDS.^S1

The benchmark covers the full chip-design flow: architecture, microarchitecture, RTL, functional verification, logic synthesis, floor planning, placement, clock-tree synthesis, routing, timing and power signoff, and physical verification.^S1 Existing RTL-only benchmarks, the source notes, typically stop before downstream physical implementation, where an RTL design can still fail timing, exceed area or power budgets, fail to route, or produce physical-design violations.^S1

Initial evaluations report that tested agents passed functional verification on about 40% of tasks on average, while only approximately 10% met the required physical performance, power and area (PPA) targets.^S1 William Wang, Founder and CEO of ChipAgents, said the benchmark gives the industry a way to measure the gap between current agents and chip-design superintelligence.^S1 Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA, said the benchmark gives developers a clear view of where reasoning and tool use must improve.^S1

The benchmark was developed by Surya Gunukula, Jerry Yicheng Wang and Kevin Zhang, with technical expertise from NVIDIA. Full task details, methodology and results are hosted at chipagents.ai/research/build-a-chip-bench.^S1

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.