5CSEBA4U19C6N vs 5CSEBA2U19C6N 比較

詳細並排比較 5CSEBA4U19C6N 由 Intel 與 5CSEBA2U19C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 5CSEBA4U19C6N 5CSEBA2U19C6N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Cyclone V SE SoC FPGA Cyclone V SE SoC FPGA
Logic Elements 40,000 (40K LE) 25 K
Hard Processor System (HPS) Dual-core ARM Cortex-A9 MPCore with CoreSight —
Maximum HPS Clock Frequency 925 MHz —
封裝 484-pin UFBGA / UBGA (19x19 mm) 484-pin UBGA (19x19 mm)
FPGA User I/O 161 (per Altera product page) —
Process Technology TSMC 28 nm low-power TSMC 28 nm low-power
Memory Controller Hard controller for DDR2 / DDR3 / LPDDR2 —
DSP Blocks Variable-precision DSP blocks (18x18 multipliers) Variable-precision DSP
Embedded Memory M10K memory blocks —
Encryption Support AES encryption (per LCSC listing) —
Error Detection SEU error detection and correction support —
工作溫度 0C to +85C (commercial grade) —
安裝類型 Surface Mount (BGA) Surface Mount
RoHS 狀態 Compliant Compliant
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Clock Frequency — 925 MHz
Operating Temperature Grade — Commercial (other)
Memory Interfaces — DDR2, DDR3, LPDDR2 with ECC
HPS Peripherals — GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC
L2 Cache — 512 KB shared
L1 Cache per Core — 32 KB I-cache + 32 KB D-cache
FPGA-to-HPS Bridges — AXI-32/AXI-64, FPGA-to-SDRAM ports

資料表與資源

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