5CSEBA5U19C6N vs 5CSEBA5U19C7N 比較

詳細並排比較 5CSEBA5U19C6N 由 Intel 與 5CSEBA5U19C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 5CSEBA5U19C6N 5CSEBA5U19C7N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Cyclone V SE SoC FPGA Cyclone V SE SoC FPGA
Logic Elements 85K 85,000
Hard Processor Cores Dual ARM Cortex-A9 MPCore with CoreSight —
Maximum HPS Clock Frequency 925 MHz —
封裝 484-UBGA (19x19 mm) 484-UBGA (UBGAmobile, 19x19 mm)
Process Technology 28 nm low-power —
Embedded Memory Approximately 4,450 Kbits (per family datasheet) M10K + MLAB blocks, ~4,450 Kbits total
DSP Blocks 87 variable-precision Variable-precision, 18x18 / 27x27 multipliers
PLLs 8 fractional —
Maximum User I/O 364 (per family datasheet) —
Peripherals CAN, USB OTG, Gigabit Ethernet, DDR3 controller, PCIe Gen2, I2C, SPI, UART —
工作溫度 Commercial (0C to +85C) per C6 speed/temp code 0C to +85C (commercial, junction)
Speed Grade C6 -7 (standard)
RoHS 狀態 Compliant (per Altera product page) —
安裝類型 Surface Mount (BGA) Surface Mount (BGA)
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Frequency — 800 MHz per core
Process Node — 28 nm low-power (TSMC)
Supply Voltage (Core) — 1.1 V typical
HPS Peripherals — EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART
RoHS / Pb-free — Yes
Configuration Memory — External (active serial via HPS or FPGA)
MSL 等級 — 3 (per JEDEC J-STD-020, reflow 260C)
Block Pins (User I/O) — Approximately 66 user I/O pins

資料表與資源

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