5M1270ZT144C4N vs 5M1270ZT144C5N 比較

詳細並排比較 5M1270ZT144C4N 由 Altera 與 5M1270ZT144C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 5M1270ZT144C4N 5M1270ZT144C5N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX V CPLD —
Logic Elements 1270 1270
Macrocells 980 980
User I/O Pins 114 —
Logic Array Blocks (LABs) 8 —
Pin-to-Pin Propagation Delay (tPD) 8.1 ns 6.2 ns
Maximum Internal Frequency 247.5 MHz 118.3 MHz
Core Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) —
Process Technology 0.18 um CMOS —
Configuration Memory Non-volatile Flash Flash (non-volatile, in-system programmable)
Programming Interface JTAG (IEEE 1149.1) - In-System Programmable JTAG in-system programmable (Altera Quartus II)
User Flash Memory (UFM) Yes (on-chip, non-volatile data storage) 8 Kbits
封裝 144-pin TQFP (22 mm x 22 mm, 0.5 mm pitch) TQFP-144 (22 x 22 mm, 0.5 mm pitch)
安裝類型 Surface Mount Surface Mount
Operating Temperature Grade Commercial (0C to +85C) —
RoHS 狀態 Compliant Compliant
Device Type — CPLD (Complex Programmable Logic Device)
Series — MAX V
User I/Os — 114
Internal Frequency (typical) — 201 MHz
VCCINT (Core Supply) — 1.71 V to 1.89 V
VCCIO (I/O Supply, per bank) — 1.2 V to 3.3 V
Number of I/O Banks — 4
Supported I/O Standards — LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins
JTAG Interface — IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1)
Program/Erase Cycles — Up to 100,000
工作溫度 — 0 C to +85 C (commercial grade)

資料表與資源

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