5M40ZM64C5N vs 5M80ZM64C5N 比較
詳細並排比較 5M40ZM64C5N 由 Altera 與 5M80ZM64C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5M40ZM64C5N | 5M80ZM64C5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX V | — |
| Device Logic Elements | 40 | — |
| Macrocells | 32 | — |
| Maximum Internal Frequency | 118.3 MHz | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| Supply Voltage - Core (VCCINT) | 1.8 V | — |
| I/O Voltage Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V tolerant | — |
| Programmable I/O Pins | 30 (approximate, per MAX V 5M40Z datasheet family) | — |
| User Flash Memory | 8 Kbits | — |
| Configuration Method | Non-volatile flash, instant-on, single-chip | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | — |
| Standby Current (ICCSTBY) | 55 µA typical | — |
| 工作溫度範圍 | 0 °C to +85 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | 64-ball MBGA, 5 mm × 5 mm | 64-MBGA |
| RoHS 狀態 | Compliant | unknown |
| 安裝類型 | Surface Mount (BGA) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture Family | — | MAX V |
| Macrocell Count | — | 64 macrocells |
| Propagation Delay | — | 7.5 ns |
| User I/O Count | — | 30 I/Os |
| Programmable Logic Type | — | FLASH |
| Technology | — | CMOS |
| Package Pin Count | — | 64 pins |
| 供應電壓 | — | [DATA_NEEDED: supply voltage] |
| I/O Standard Support | — | [DATA_NEEDED: supported I/O standards] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |
| JTAG Support | — | [DATA_NEEDED: JTAG support] |