A42MX09-2PLG84I vs A42MX24-2PLG84I 比較
詳細並排比較 A42MX09-2PLG84I 由 Microchip Technology 與 A42MX24-2PLG84I 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ 啟用中規格比較
| 參數 | A42MX09-2PLG84I | A42MX24-2PLG84I |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MX (42MX) | MX (42MX) |
| System Gates | 14000 | 36000 gates |
| User I/O Pins | 72 | — |
| Logic Cells | 336 | 912 cells |
| Core Supply Voltage | 4.5 V to 5.5 V | — |
| I/O Supply Voltage | 3 V to 3.6 V (dual supply) | — |
| Speed Grade | -2 | -2 |
| Clock-to-Out | 5.6 ns | — |
| Dual-Port SRAM Access Time | 5 ns | — |
| Dual-Port SRAM | Up to 2.5 kbits configurable | — |
| Maximum Performance | 250 MHz | — |
| 工作溫度 | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| 封裝 | 84-PLCC (J-Lead), surface mount | 84-PLCC (J-Lead) |
| 安裝類型 | Surface Mount | Surface Mount |
| Process Technology | 0.45 um | — |
| RoHS 狀態 | Lead Free | Lead Free (per Kynix listing) |
| Number of Logic Blocks | [DATA_NEEDED: number of logic blocks] | — |
| User I/O | — | 72 |
| Technology | — | 0.45 um antifuse |
| Core Architecture Voltage | — | 5.0 V |
| I/O Voltage Support | — | 3.3 V / 5.0 V mixed |
| Programmability | — | One-Time Programmable (antifuse) |
| Configuration | — | No external boot device required |
| Dedicated Decode Blocks | — | D-modules (wide-input AND, CPLD-like) |
| Packaging | — | Tray |
| Primary Applications | — | ASIC alternative, legacy PLD integration |