CDK2307CILP64 vs CDK1307CILP40 比較
詳細並排比較 CDK2307CILP64 由 MaxLinear 與 CDK1307CILP40 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | CDK2307CILP64 | CDK1307CILP40 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Manufacturer | MaxLinear (formerly Exar / Cadeka) | MaxLinear (formerly Exar/Cadeka) |
| Part Number | CDK2307CILP64 | CDK1307CILP40 |
| 功能 | Dual-channel Analog-to-Digital Converter (ADC) | Analog-to-Digital Converter (ADC) |
| Number of Channels | 2 | — |
| 解析度 | 12-bit / 13-bit | 12-bit / 13-bit selectable |
| Maximum Sample Rate | 80 MSPS (12-bit), 65 MSPS (13-bit) | — |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS | — |
| Converter Architecture | Pipelined with digital error correction | — |
| Input Type | Differential analog inputs | Single-ended analog input |
| Digital Output | Parallel CMOS | — |
| Data Interface | CMOS parallel | — |
| Reference Type | Internal (on-chip) | — |
| 封裝 | 64-pin QFN (LP64) with exposed pad | 40-pin LQFP (LP) |
| 安裝類型 | Surface Mount | — |
| Packaging | Tray | — |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| Sample Rate | — | 65 MSPS (family supports 20/40/65/80 MSPS) |
| Architecture | — | Multi-stage pipeline with digital error correction |
| Full-Scale Input Range | — | 1 Vpp typical |
| Supply Voltage (Analog) | — | 3.3 V |
| Supply Voltage (Digital) | — | 3.3 V |
| Reference | — | Internal (1.2 V bandgap) |
| Output Interface | — | Parallel CMOS |
| Control Interface | — | CMOS serial configuration |
| 工作溫度 | — | -40 C to +85 C (industrial) |